公开(公告)号：EP4181408A1

公开(公告)日：2023-05-17

申请号：EP21874120.5

申请日：2021-08-19

申请人： ZTE Corporation

发明人： ZHANG, Xingmin ,  WEI, Zhaobi ,  WANG, Shan ,  JIANG, Yuting

IPC分类号： H04B1/50 ,  H04B17/11 ,  H04B17/21

摘要： A communication device, a control method, a base station and a computer-readable storage medium. The communication device comprises a transmitting link, a receiving link, an antenna module, a coupling module, a correction frequency conversion module and a logic module, wherein the antenna module is respectively connected to the transmitting link and the receiving link; the coupling module is respectively connected to the transmitting link, the receiving link and the antenna module; the correction frequency conversion module is arranged on the transmitting link and/or the receiving link; when the correction frequency conversion module is arranged on the transmitting link, the correction frequency conversion module is controlled to work, the transmitting link can transmit a first correction signal of a second frequency point, and the receiving link can receive the first correction signal and transmit same to the logic module to correct a radio frequency signal; and when the correction frequency conversion module is arranged on the receiving link, the transmitting link can transmit a second correction signal of a first frequency point, and the correction frequency conversion module is controlled to work, such that the receiving link can receive the second correction signal and transmit same to the logic module to correct the radio frequency signal.

公开(公告)号：EP4167507A1

公开(公告)日：2023-04-19

申请号：EP21822239.6

申请日：2021-06-02

申请人： ZTE Corporation

发明人： ZHU, Shaofei ,  WEI, Zhaobi

IPC分类号： H04L1/00

摘要： Provided are a data transmission method and apparatus, a circuit board, a storage medium and an electronic apparatus. The method is applied between a chip and an analog-to-digital/digital-to-analog conversion device, and comprises: transmitting first data by means of a first transmission channel, wherein the first transmission channel comprises an invalid bit in a second transmission channel, the second transmission channel is a transmission channel for transmitting second data, the first data comprises custom data, and the second data comprises service data (S202).

公开(公告)号：EP3998719A1

公开(公告)日：2022-05-18

申请号：EP20836462.0

申请日：2020-07-06

申请人： ZTE Corporation

发明人： LIU, Jun ,  WEI, Zhaobi ,  WANG, Shan ,  LEI, Mengbi ,  ZHANG, Guojun

IPC分类号： H04J3/06

摘要： Provided in the embodiments of the present invention are a phase detection method and apparatus for a clock signal, and a communication device. A clock signal of a clock to be detected is sampled according to sampling periods set by a sampling clock; a phase angle value corresponding to a sampled clock signal in a current sampling period is obtained according to a mapping relationship between sampled signals and phase angle values; a phase difference corresponding to the current sampling period is subtracted from the phase angle value to obtain an initial phase value of the clock to be detected in the current sampling period, wherein the phase difference is a phase difference between the clock to be detected and the sampling clock in the current sampling period; and after the sampling ends, a final phase value of the clock to be detected is obtained according to initial phase values obtained in respective sampling periods. Since the final phase value is obtained according to the initial phase values obtained in multiple sampling periods, the obtained final phase value has higher accuracy and better fault tolerance.

公开(公告)号：EP3993334A1

公开(公告)日：2022-05-04

申请号：EP20834640.3

申请日：2020-07-03

申请人： ZTE Corporation

发明人： HE, Haitao ,  WEI, Zhaobi ,  LI, Xiaofei ,  LI, Congwei

IPC分类号： H04L27/26

摘要： The embodiments of the present invention provide a signal processing method, apparatus and device, and a computer readable storage medium. Said method comprises: processing multiple types of bandwidth signals to be sent, to form multiple groups of standard bandwidth signals; filtering the multiple groups of standard bandwidth signals; and combining the filtered multiple groups of standard bandwidth signals and transmitting same. In the embodiments of the present invention, multiple types of bandwidth signals are processed to form multiple groups of standard bandwidth signals, so that a DUC/DDC can use uniform processing architecture which has high reusability and high flexible extensibility, reducing the processing complexity and design redundancy of the DUC/DDC, achieving a simpler and more consistent structure, and reducing the costs and heat consumption of a digital intermediate frequency chip.

公开(公告)号：EP3989442A1

公开(公告)日：2022-04-27

申请号：EP20835431.6

申请日：2020-06-19

申请人： ZTE Corporation

发明人： LIU, Jun ,  WEI, Zhaobi ,  WANG, Shan ,  DUAN, Pei ,  LEI, Mengbi

IPC分类号： H03L7/099

摘要： The present disclosure provides a phase-locked loop circuit, a configuration method therefor, and a communication apparatus. The phase-locked loop circuit comprises: a phase-locked loop main circuit; and a phase temperature compensation circuit capable of configuring, according to a phase shift generated by the phase-locked main circuit as a result of a temperature change, at least one phase delay unit of the phase temperature compensation circuit to be connected to the phase-locked loop main circuit, and cancelling out, by using a phase shift generated by the connected phase delay unit of the phase temperature compensation circuit as a result of the temperature change, the phase shift generated by the phase-locked loop main circuit as a result of the temperature change. In this way, the invention ensures the phase-locked loop circuit does not generate a phase shift as result of a temperature change or only generates a phase shift in a small range during operations thereof. When the invention is applied to multi-channel communication, a phase difference between channels is kept at the minimum at all times since a temperature change causes no phase shift or only a phase shift in a small range for the phase-locked loop circuits of the channels, thereby essentially meeting a synchronization requirement.