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    Data acquisition systems with programmable bit-serial digital signal processors
    4.
    发明公开
    Data acquisition systems with programmable bit-serial digital signal processors 失效
    具有可编程位串行数字信号处理器的数据采集系统

    公开(公告)号：EP0498953A3

    公开(公告)日：1994-01-12

    申请号：EP91120966.6

    申请日：1991-12-06

    申请人： Yokogawa Electric Corporation

    发明人： Garverick, Steven Lee ,  Fujino, Kenji

    IPC分类号： G06F15/78 ,  G01R21/133 ,  G06F7/544 ,  G06F15/31

    CPC分类号： G06F15/7842 ,  G01R21/006 ,  G05B19/0423 ,  G05B2219/25254 ,  G06F7/5443 ,  G06F7/5446

    摘要： A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.

    摘要翻译： 单片集成电路可与用于产生相应传感器输出信号的多个传感器结合使用，所述单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置，以及一些初始处理电路，所述初始处理电路包括位 - 串行乘加处理器。 该处理器包括位串行数字乘法器，用于将第一数字处理器输入信号以位串行形式与第二数字处理器输入信号相乘以生成数字乘积信号;数字加法器，用于将第三数字处理器输入信号添加到数字 产生信号以产生数字和信号，以及用于向数字处理器输出信号提供对应于所述数字和信号的位的装置。 存储器系统提供用于存储程序指令的存储器，用于存储第二数字处理器输入信号的连续值的存储器，用于存储第三数字处理器输入信号的连续值的存储器以及用于存储被写入的数字处理器输出信号的连续值的存储器 进入内存系统。 第一数字处理器输入信号可以从传感器输出信号中选择，并转换成位串行数字格式。 施加到位串行乘加处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间处，以及施加到位串行乘加处理器的第三数字处理器输入信号。 控制器以规定的顺序从用于存储程序指令的存储器中检索存储的程序指令，并产生用于至少控制存储器系统的读写的控制信号，以及选择第一数字处理器输入信号。

    Integrated skid with multiple-motor controller
    7.
    发明公开
    Integrated skid with multiple-motor controller 有权
    IntegrierterTrägermit mehrmotorigem Regler

    公开(公告)号：EP1596263A1

    公开(公告)日：2005-11-16

    申请号：EP05252009.5

    申请日：2005-03-31

    申请人： Hamilton Sundstrand Corporation

    发明人： Marks, Kenneth ,  Parsons, Douglas A.

    IPC分类号： G05B19/042 ,  F04C15/00

    CPC分类号： G05B19/042 ,  G05B2219/25254

    摘要： An integrated skid system (100) integrates the functions of multiple skids (101) into a single skid (102) to reduce the skid footprint and the complexity of the overall system. A multi-motor controller (104) monitors the devices (101) on the integrated skid (100) to maintain proper temperature, pressure and current draw in the devices (101). Based on this information, the multi-motor controller (104) can make decisions on faults and fault accommodation and communicate with a main controller (120) regarding the operating states of the skid devices (101) via a single serial or Ethernet-type connection (122).

    摘要翻译： 集成滑道系统（100）将多个滑行（101）的功能集成到单个滑道（102）中，以减少滑行占地面积和整个系统的复杂性。 多电动机控制器（104）监视集成滑板（100）上的装置（101）以在装置（101）中保持适当的温度，压力和电流消耗。 基于该信息，多马达控制器104可以通过单个串行或以太网类型连接来做出关于故障和故障调节的决定并与主控制器（120）通信关于滑动设备（101）的操作状态 （122）。

    Data acquisition systems with programmable bit-serial digital signal processors
    8.
    发明公开
    Data acquisition systems with programmable bit-serial digital signal processors 失效
    Datenerfassungssystem mit programmierbaren bitseriellen digitalen Signal-Prozessoren。

    公开(公告)号：EP0498953A2

    公开(公告)日：1992-08-19

    申请号：EP91120966.6

    申请日：1991-12-06

    申请人： Yokogawa Electric Corporation

    发明人： Garverick, Steven Lee ,  Fujino, Kenji

    IPC分类号： G06F15/78 ,  G01R21/133 ,  G06F7/544 ,  G06F15/31

    CPC分类号： G06F15/7842 ,  G01R21/006 ,  G05B19/0423 ,  G05B2219/25254 ,  G06F7/5443 ,  G06F7/5446

    摘要： A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.

    摘要翻译： 可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路，该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置，以及一些初始处理电路，包括一位 - 系列乘法加法处理器。 该处理器包括位串行数字乘法器，用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器，用于将第三数字处理器输入信号加到数字 产生信号以产生数字和信号，以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。 存储器系统提供用于存储程序指令的存储器，用于存储第二数字处理器输入信号的连续值的存储器，用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器， 进入内存系统。 可以从传感器输出信号中选择第一个数字处理器输入信号，转换为位串行数字格式。 应用于位串行加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间，以及施加到位串行多重加法处理器的第三数字处理器输入信号。 控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令，并且生成用于至少控制存储器系统的读取和写入以及选择第一数字处理器输入信号的控制信号。