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    METHOD FOR THE CONTINUOUS MONITORING AND DIAGNOSIS OF SOURCES OF PARTIAL DISCHARGES (PDs) IN HIGH-VOLTAGE CABLES DURING CONNECTION TO, AND OPERATION IN THE POWER GRID, AND PHYSICAL SYSTEM FOR CARRYING OUT SAME
    1.
    发明公开
    METHOD FOR THE CONTINUOUS MONITORING AND DIAGNOSIS OF SOURCES OF PARTIAL DISCHARGES (PDs) IN HIGH-VOLTAGE CABLES DURING CONNECTION TO, AND OPERATION IN THE POWER GRID, AND PHYSICAL SYSTEM FOR CARRYING OUT SAME 审中-公开
    方法连续监测和局部放电高压电缆来源的诊断期间的连接，以及建立电网与物理实现系统

    公开(公告)号：EP2579055A1

    公开(公告)日：2013-04-10

    申请号：EP11789287.7

    申请日：2011-05-24

    Applicant: Universidad Politécnica de Madrid ,  Union Fenosa Distribucion, S.A.

    Inventor： GARNACHO LÓPEZ, D.Fernando ,  SANCHEZ URAN, Miguel Angel ,  ORTEGO LA MONEDAY, Javier

    IPC: G01R31/08

    CPC classification number: G06F17/148 ,  G01R31/021 ,  G01R31/083 ,  G01R31/088 ,  G01R31/1272 ,  G06F17/18

    Abstract: The invention relates to a method specially designed for detecting events associated with partial discharges (PDs) in high voltage cables, comprising the identification of the location and the evaluation of the amplitude and rate of repetition per period of the grid voltage, with the possibility of identifying different sources producing PD signals as a function of the location thereof and recognising the type of defect associated with PDs in the same location, including the measurement of the generated electric signals and the discrimination thereof in relation to the background noise. The invention also relates to a system for carrying out said method, comprising means for discriminating the noise in relation to the transient waveform of the PD, determining the parameters associated therewith, determining the map of sources of PDs along the length of the cable, graphically representing said sources, and identifying the patterns of the sources of PDs separated as a function of the location thereof along the length of the cable.

    Abstract translation: 本发明涉及一种特别设计用于检测与在高压电缆的局部放电（PDS）相关联的事件，包括所述位置的识别和振幅和每电网电压的重复周期的比率的评价的方法，用的可能性 识别不同来源生产PD信号作为位置的函数和其识别缺陷的与PD在相同的位置相关联的类型，包括所产生的电信号的测量并相对于背景噪声其鉴别。 因此本发明涉及一种系统，用于执行该方法，包括用于在关系辨别噪声对PD的瞬态波形，具有，确定性采矿相关联的确定性采矿的参数有沿着电缆的长度PD的源的地图，图形 表示所述源和识别的分离为沿着电缆的长度及其位置的函数PD的源的图案。

    A 2D FIFO device and method for use in block based coding applications
    5.
    发明公开
    A 2D FIFO device and method for use in block based coding applications 有权
    对于基于块的编码以及它们的方法的2D FIFO装置

    公开(公告)号：EP1296288A3

    公开(公告)日：2005-03-09

    申请号：EP02447181.5

    申请日：2002-09-23

    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW

    Inventor： Lafruit, Gauthier ,  Masschelein, Bart

    IPC: G06T9/00 ,  G06T1/00

    CPC classification number: H04N19/426 ,  G06F17/148 ,  G06T5/20 ,  H04N19/42 ,  H04N19/63 ,  H04N19/645

    Abstract: Coding, transcoding and iterative filtering methods and apparatus are described using a concept of a 2D FIFO to implement a CACLA processing. The processing methods are block-oriented. A block-by-block processed input image or input coded image which is delayed in an arbitrary number of lines and columns is provided, in such a way that the output image is still produced in a block-by-block schedule, at a reduced or minimal memory access and memory size cost. A 2D FIFO, being memory-efficient (hence at a minimal memory (access and size) cost) in image block coding and decoding applications is described. The 2D FIFO is a device having an associated scheduling mechanism used for enabling delaying of a block-by-block coded input signal such as an image (e.g. a JPEG, JPEG2000, MPEG-4 or similar image) in an arbitrary number of lines and columns, in such a way that the output image is still produced in a block-by-block schedule. The 2D FIFO tailored memory schedule mechanism can achieve the realignment process at reduced or minimal memory (access and size) cost. The process is functionally identical to delaying the rows and columns of the input image along a set of horizontal and vertical FIFOs, except that the pixels remain clustered in blocks rather than lines.

    ARCHITECTURES FOR DISCRETE WAVELET TRANSFORMS
    7.
    发明公开
    ARCHITECTURES FOR DISCRETE WAVELET TRANSFORMS 有权
    体结构的离散小波变换

    公开(公告)号：EP1412911A1

    公开(公告)日：2004-04-28

    申请号：EP02724362.5

    申请日：2002-05-28

    Applicant: Nokia Corporation

    Inventor： GUEVORKIAN, David ,  LIUHA, Petri ,  LAUNIAINEN, Aki, Juhana ,  LAPPALAINEN, Ville

    IPC: G06K9/36 ,  H04N7/26 ,  G06T9/00

    CPC classification number: H04N19/63 ,  G06F17/148 ,  G06T1/20 ,  H04N19/42

    Abstract: A microprocessor structure for performing a discrete wavelet transform operation, said discrete wavelet transform operation comprising decomposition of an input signal comprising a vector of r x km input samples, r, k and m being non-zero positive integers, over a specified number of decomposition levels j, where j is an integer in the range 1 to J, starting from a first decomposition level and progressing to a final decomposition level, said microprocessor structure having a number of processing stages, each of said number of processing stages corresponding to a decomposition level j of the discrete wavelet transform operation and being implemented by a number of basic processing elements, the number of basic processing elements implemented in each of said processing stages decreasing by a factor of k from a decomposition level j to a decomposition level j+1.

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