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    Circuitry for carrying out at least one of a square root operation and a division operation
    2.
    发明公开
    Circuitry for carrying out at least one of a square root operation and a division operation 有权
    电路用于执行平方根操作的至少一个，并且分

    公开(公告)号：EP1315081A1

    公开(公告)日：2003-05-28

    申请号：EP01309854.6

    申请日：2001-11-22

    申请人： STMicroelectronics, Ltd.

    发明人： Kurd, Tariq

    IPC分类号： G06F7/52 ,  G06F7/552

    CPC分类号： G06F7/535 ,  G06F7/5525

    摘要： The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry comprises a carry save adder, and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in parallel.

    摘要翻译： 本发明提供了用于执行平方根手术中的至少一个和一个除法运算电路。 所述电路包括一个进位保存加法器和进位传送加法器部分。 进位保存加法器和进位加法器繁殖部分平行布置。

    Circuit for calculation of division and square root with floating point numbers
    3.
    发明公开
    Circuit for calculation of division and square root with floating point numbers 审中-公开
    Schaltung zum Berechnen von Division und Quadratwurzel mit Gleitkommazahlen

    公开(公告)号：EP1315079A1

    公开(公告)日：2003-05-28

    申请号：EP01309849.6

    申请日：2001-11-22

    申请人： STMicroelectronics, Ltd.

    发明人： Kurd, Tariq

    IPC分类号： G06F7/52 ,  G06F7/552

    CPC分类号： G06F7/535 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/5528

    摘要： The invention provides circuitry for carrying out an arithmetic operation requiring a plurality of iterations. The circuitry comprises N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry comprises at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.

    摘要翻译： 本发明提供用于执行需要多次迭代的算术运算的电路。 该电路包括一组相继布置的N组迭代电路，使得迭代电路组中的至少一个接收来自迭代电路组之前的一组的输出。 迭代电路组中的每一个包括至少一个加法器部分，其中全加器由迭代电路组之一中的至少一个部分提供，并且迭代电路组中的后一组中的第二部分。

    Arithmetic processing apparatus and method used thereby
    6.
    发明公开
    Arithmetic processing apparatus and method used thereby 失效
    ArthmetischesVerarbeitungsgerätund dazu benutztes Verfahren

    公开(公告)号：EP0723218A2

    公开(公告)日：1996-07-24

    申请号：EP96103447.7

    申请日：1990-10-16

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

    发明人： Taniguchi, Takashi

    IPC分类号： G06F7/02

    CPC分类号： G06F7/535 ,  G06F7/026 ,  G06F7/4873 ,  G06F7/49952 ,  G06F7/49957 ,  G06F7/544 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F2207/5356

    摘要： An approximate solution Ya of a function F with respect to a given value X is derived by referring to a relation Y=F(X) at an accuracy at which an error between the approximate solution Ya and an infinitely precise solution Y is smaller than a weight of a digit in a place lower than a lowest place of significant digits for a final solution by two places. The approximate solution Ya is rounded to an interim solution Yr equal to one of possible interim solutions which is closest to the approximate solution Ya. A value Xr is derived from the interim solution Yr and an inverse function F -1 by referring to a relation Xr=F -1 (Yr) . A sticky digit S is set to 0, 1, or -1 in response to the relation between the magnitudes of the values X and Xr and other information. The sticky digit S is added to a place immediately lower than a lowest place of the interim solution Yr. A result of this addition is rounded in a designated rounding mode to obtain the final solution.
    An apparatus may be used for multiplying two numbers and subtracting a third number from the resulting product.

    摘要翻译： 通过以近似解Ya和无限精确解Y之间的误差小于1的精度参考关系Y = F（X）导出关于给定值X的函数F的近似解Ya 在比最终解决方案的两个地方低一个有效数字最低位置的地方的数字的权重。 近似解Ya被四舍五入到等于最接近近似解Ya的可能临时解之一的临时解。 通过参照关系Xr = F <-1）导出值Xr。 响应于值X和Xr的大小与其他信息之间的关系，粘性数字S被设置为0,1或者-1。 粘性数字S被添加到立即低于临时解决方案Yr的最低位置的地方。 这种添加的结果以指定的舍入模式舍入，以获得最终解决方案。 可以使用装置来乘以两个数字，并从所得到的乘积中减去第三个数字。

    Arithmetic processing apparatus and method used thereby
    7.
    发明公开
    Arithmetic processing apparatus and method used thereby 失效
    算术处理设备及其使用的方法

    公开(公告)号：EP0424086A3

    公开(公告)日：1992-09-09

    申请号：EP90311315.7

    申请日：1990-10-16

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Taniguchi, Takashi

    IPC分类号： G06F7/544 ,  G06F7/52 ,  G06F7/552

    CPC分类号： G06F7/535 ,  G06F7/026 ,  G06F7/4873 ,  G06F7/49952 ,  G06F7/49957 ,  G06F7/544 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F2207/5356

    摘要： An approximate solution Ya of a function F with respect to a given value X is derived by referring to a relation Y=F(X) at an accuracy at which an error between the approximate solution Ya and an infinitely precise solution Y is smaller than a weight of a digit in a place lower than a lowest place of significant digits for a final solution by two places. The approximate solution Ya is rounded to an interim solution Yr equal to one of possible interim solutions which is closest to the approximate solution Ya. A value Xr is derived from the interim solution Yr and an inverse function F⁻¹ by referring to a relation Xr=F⁻¹(Yr). A sticky digit S is set to 0, 1, or -1 in response to the relation between the magnitudes of the values X and Xr and other information. The sticky digit S is added to a place immediately lower than a lowest place of the interim solution Yr. A result of this addition is rounded in a designated rounding mode to obtain the final solution.

    METHOD AND PROCESSOR FOR HIGH-SPEED CONVERGENCE FACTOR DETERMINATION
    8.
    发明公开
    METHOD AND PROCESSOR FOR HIGH-SPEED CONVERGENCE FACTOR DETERMINATION 失效
    高速处理及收敛处理器，用于确定因子。

    公开(公告)号：EP0461230A1

    公开(公告)日：1991-12-18

    申请号：EP91901464.0

    申请日：1990-12-03

    申请人： MOTOROLA, INC.

    发明人： LINDSLEY, Brett, Louis

    IPC分类号： G06F7

    CPC分类号： G06F7/535 ,  G06F7/4873 ,  G06F7/5525 ,  G06F2207/5355

    摘要： Un processeur ultra-rapide utilise une logique combinatoire et une limitation de plage pour une valeur d'entrée modifiée, en vue d'augmenter l'efficacité de la détermination du facteur de convergence pour la division convergente et la calcul de la racine carrée. Une valeur d'entrée (101) est modifiée pour obtenir une certaine valeur dans une plage limitée (104), qui est ensuite divisée en deux subdivisions (106, 108). A l'aide de ces deux groupements, le programme de traitement réduit au minimum le temps nécessaire pour déterminer le facteur de conversion en inversant les bits binaires sélectionnés pour former un facteur modifié (114), et le programme utilise ensuite ce facteur modifié pour faciliter le calcul ultra-rapide du facteur de convergence.

    Floating point arithmetic units
    10.
    发明公开
    Floating point arithmetic units 失效
    浮点算术单位

    公开(公告)号：EP0351242A3

    公开(公告)日：1991-09-11

    申请号：EP89307180.3

    申请日：1989-07-14

    申请人： FUJITSU LIMITED

    发明人： Katsuno, Akira

    IPC分类号： G06F7/52 ,  G06F7/552

    CPC分类号： G06F7/535 ,  G06F7/4873 ,  G06F7/49936 ,  G06F7/49957 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F2207/5356

    摘要： In a floating point arithmetic unit an iterative binary arithmetic operation is performed upon two operands (D₁, D₂) applied to the unit in floating point form. The unit includes respective operating portions for deriving mantissa, exponent and sign components of the desired result (D₃) respectively, the mantissa operating portion including fixed point multiplication means (10) for multiplying together the respective mantissa components of the two operands concerned, and subtraction means (41, 42, 15) operative, in each cycle of the iterative operation, to form the inverse of the fractional part of a binary number derived from the output of the said multiplication means (10) and to increment that inverse by adding one to the least significant bit thereof. The use of such a floating point arithmetic unit can enable division and square root operations, for example, to be performed at high speed and with desirably high accuracy.