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    Signal processing arrangement
    1.
    发明公开
    Signal processing arrangement 失效
    Anordnung zur Signalverarbeitung。

    公开(公告)号：EP0167677A1

    公开(公告)日：1986-01-15

    申请号：EP84201049.8

    申请日：1984-07-13

    申请人： BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  ALCATEL N.V.

    发明人： Dierckx, Rudolf ,  Sallaerts, Daniel ,  Guebels, Pierre-Paul

    IPC分类号： H04B3/23 ,  G06F15/336 ,  H03H21/00

    CPC分类号： H04B3/23 ,  H03H21/0012 ,  H03H2220/06 ,  H04B3/238

    摘要： The signal processing arrangement is an adaptive digital filter comprising a digital filter coefficient updating circuit (CUC) which supplies updated filter coefficients to a digital filter circuit proper (FC) and is controlled by an error signal (E) derived from the output signal of the filter proper. Each of these two circuits (CUC, FC) is constituted by a systolic processor with a plurality of interconnected cells each able to calculates a function of the type mn + p in a bit serial way and in such a way that bits of a same rank are successively calculated in the cells starting from right to left.

    摘要翻译： 信号处理装置是一种自适应数字滤波器，包括一个数字滤波器系数更新电路（CUC），该数字滤波器系数更新电路（CUC）将更新的滤波器系数提供给数字滤波器电路（FC），并由一个由 过滤适当。 这两个电路（CUC，FC）中的每一个由具有多个互连的单元的收缩处理器构成，每个互连单元能够以串行方式计算类型mn + p的功能，并且以这样的方式使相同排的位 在从右到左的单元格中连续计算。

    MULTI-BRANCH DOWN CONVERTING FRACTIONAL RATE CHANGE FILTER
    2.
    发明公开
    MULTI-BRANCH DOWN CONVERTING FRACTIONAL RATE CHANGE FILTER 审中-公开
    美孚VERZWEIGTERABWÄRTSUMWANDLUNGSFILTERMIT NICHTGANZZAHLIGERRATENÄNDERUNG

    公开(公告)号：EP3055928A1

    公开(公告)日：2016-08-17

    申请号：EP14781669.8

    申请日：2014-07-25

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： HIND, Joleen ,  LAPORTE, Pierre-Andre

    IPC分类号： H03H17/02 ,  H03H17/06

    CPC分类号： H04L25/0262 ,  H03H17/0275 ,  H03H17/0416 ,  H03H17/0621 ,  H03H17/0685 ,  H03H2220/06

    摘要： A method of filtering an input sample stream having a downsampling rate is disclosed to generate an output sample stream having an upsampling rate that is less than the downsampling rate. The input sample stream is input to a rate change filter having multiple filter branches. The input sample stream is filtered at each of the multiple filter branches to output filtered sample substreams. Each of the multiple filter branches have filter coefficients corresponding to a different phase of the filter response. The filtered sample substreams are stored in a memory and the stored filtered sample substreams are combined to generate the output sample stream.

    摘要翻译： 公开了一种对具有下采样率的输入采样流进行滤波的方法，以产生具有小于下采样率的上采样率的输出采样流。 输入采样流被输入到具有多个滤波器分支的速率变化滤波器。 输入样本流在多个滤波器分支中的每一个处进行滤波以输出滤波后的样本子流。 多个滤波器分支中的每一个具有对应于滤波器响应的不同相位的滤波器系数。 将经过滤的样本子流存储在存储器中，并且存储的过滤样本子流被组合以产生输出样本流。

    RESOURCE-SAVING CIRCUIT STRUCTURES FOR DEEPLY PIPELINED SYSTOLIC FINITE IMPULSE RESPONSE FILTERS
    3.
    发明公开
    RESOURCE-SAVING CIRCUIT STRUCTURES FOR DEEPLY PIPELINED SYSTOLIC FINITE IMPULSE RESPONSE FILTERS 审中-公开
    RESSOURCENSPARENDE SCHALTUNGSSTRUKTURENFÜRTIEF GIPIPELINTE SYSTOLISCHE过滤器麻省理工学院

    公开(公告)号：EP3104524A2

    公开(公告)日：2016-12-14

    申请号：EP16169462.5

    申请日：2016-05-12

    申请人： Altera Corporation

    发明人： Langhammer, Martin ,  Finn, Simon Peter

    IPC分类号： H03H17/06

    CPC分类号： H03H17/06 ,  G06F7/5443 ,  H03H2220/04 ,  H03H2220/06

    摘要： Circuitry that accepts a data input (420) and an enable input (425), and generates an output sum (424) based on the data input includes an input stage circuit that includes an input register (401). The input register (401) accepts the enable input (425). The circuitry further includes a systolic register (413) operatively connected to the input stage circuit, and the systolic register (413) is operated without any enable connection. The circuitry further includes a multiplier (406) connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder (416) that calculates the output sum based least in part on the product value.

    摘要翻译： 接受数据输入（420）和使能输入（425）的电路，并且基于数据输入生成输出和（424）包括输入级电路，其包括输入寄存器（401）。 输入寄存器（401）接受使能输入（425）。 电路还包括可操作地连接到输入级电路的收缩期寄存器（413），并且在没有任何使能连接的情况下操作收缩寄存器（413）。 电路还包括连接到收缩寄存器的乘法器（406），其被配置为产生乘积值。 电路还包括输出级电路，其包括加法器（416），该加法器至少部分地基于乘积值来计算输出总和。

    RESOURCE-SAVING CIRCUIT STRUCTURES FOR DEEPLY PIPELINED SYSTOLIC FINITE IMPULSE RESPONSE FILTERS
    4.
    发明公开
    RESOURCE-SAVING CIRCUIT STRUCTURES FOR DEEPLY PIPELINED SYSTOLIC FINITE IMPULSE RESPONSE FILTERS 审中-公开
    深层流体有限冲击响应滤波器的资源节约电路结构

    公开(公告)号：EP3104524A3

    公开(公告)日：2017-04-26

    申请号：EP16169462.5

    申请日：2016-05-12

    申请人： Altera Corporation

    发明人： Langhammer, Martin ,  Finn, Simon Peter

    IPC分类号： H03H17/06

    CPC分类号： H03H17/06 ,  G06F7/5443 ,  H03H2220/04 ,  H03H2220/06

    摘要： Circuitry that accepts a data input (420) and an enable input (425), and generates an output sum (424) based on the data input includes an input stage circuit that includes an input register (401). The input register (401) accepts the enable input (425). The circuitry further includes a systolic register (413) operatively connected to the input stage circuit, and the systolic register (413) is operated without any enable connection. The circuitry further includes a multiplier (406) connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder (416) that calculates the output sum based least in part on the product value.

    摘要翻译： 接受数据输入（420）和使能输入（425）并且基于数据输入生成输出和（424）的电路包括包括输入寄存器（401）的输入级电路。 输入寄存器（401）接受使能输入（425）。 该电路还包括可操作地连接到输入级电路的收缩期寄存器（413），并且收缩期寄存器（413）在没有任何启用连接的情况下被操作。 该电路还包括连接到收缩注册器的乘法器（406），其被配置为生成乘积值。 该电路还包括输出级电路，该输出级电路包括加法器（416），该加法器至少部分地基于产品值来计算输出和。