利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.009 秒)

    DIGITAL LOOP SYNCHRONIZATION CIRCUIT.
    1.
    发明公开
    DIGITAL LOOP SYNCHRONIZATION CIRCUIT. 失效
    数字电路FOR循环同步。

    公开(公告)号：EP0033337A4

    公开(公告)日：1982-01-08

    申请号：EP80901606

    申请日：1981-02-24

    申请人： WESTERN ELECTRIC CO

    发明人： BAXTER LESLIE ALAN ,  CUMMISKEY PETER

    IPC分类号： H03J3/06 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L12/42 ,  H04Q11/04 ,  H04J3/07

    CPC分类号： H04L12/422 ,  H04J3/0626 ,  H04Q11/04

    摘要： Digital loop circuit for controlling synchronization around a closed loop communication system. The control circuit (20) is designed to automatically adjust the delay of the loop to maintain a constant frame bit length without regard to the number of stations connected into the loop. As stations are added or subtracted from the loop, the system operates to subtract or add delay as necessary. A first in and first out (FIFO) register having a bit capacity equal to the frame size is inserted serially in the loop and a separate clock is used to control the input and the output of the first in and first out register (FIFO). If a unique frame bit is not received in the anticipated position then the clock output skips one count per frame thereby adding delay to the loop. The loop control circuit operates for situations where the framing bit is on a separate channel and also when the framing bit is on the actual data channel.

    Low noise, high linearity TV tuner architecture with switched fixed-gain LNA
    4.
    发明公开
    Low noise, high linearity TV tuner architecture with switched fixed-gain LNA 有权
    低噪声电视调谐器结构具有高线性和开关固定增益LNA

    公开(公告)号：EP1783907A1

    公开(公告)日：2007-05-09

    申请号：EP06017187.3

    申请日：2006-08-17

    申请人： Quantek, Inc.

    发明人： Tseng, Chao-Wen ,  Lau, Wai

    IPC分类号： H03J3/06 ,  H03F1/02

    CPC分类号： H03J3/06 ,  H03F1/0277 ,  H03F2200/294 ,  H03F2200/372 ,  H03G1/0088 ,  H04B1/16

    摘要： A TV tuner (100,200) includes a plurality of amplifiers (120,122,220,222,224,226) having inputs for coupling to an antenna (110,210), a plurality of filters (140,142,230,232,234,236) having inputs coupled to outputs of the plurality of amplifiers (120,122,220,222,224,226), and a first multiplexer (150,240) having inputs coupled to outputs of the plurality of filters (140,142,230,232,234,236), the first multiplexer (150,240) for selecting an output of one of the filters (140,142,230,232,234,236). The TV tuner (100,200) further includes a mixer (160,250) having an input coupled to an output of the first multiplexer (150,240), and an output amplifier (180,270) having an input coupled to an output of the mixer (160,250) and an output for providing output of the TV tuner (100,200).

    摘要翻译： 电视调谐器（100,200）包括放大器的具有用于耦合输入到天线（110,210）耦合到放大器的多元性（120,122,220,222,224,226）的输出具有输入多个（120,122,220,222,224,226），滤波器有多个（140,142,230,232,234,236），和第一多路复用器 （150.240），具有耦合到滤波器的多元性（140,142,230,232,234,236），所述第一多路复用器（150.240）的输出，用于在所述过滤器之一（140,142,230,232,234,236）的输出选择的输入。 TV调谐器（100,200）进一步包括混频器（160.250）在所述第一多路转换器（150.240）的输出耦合到输入具有上，并且输出放大器（180.270），其具有以在混频器（160.250）的输出耦合到输入和 输出用于提供所述的电视调谐器（100,200）的输出。

    Signal receiver with tuning circuits
    6.
    发明公开
    Signal receiver with tuning circuits 失效
    信号接收器调整。

    公开(公告)号：EP0208470A2

    公开(公告)日：1987-01-14

    申请号：EP86304933.4

    申请日：1986-06-25

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Sakashita, Seiji ,  Fukui, Kiyotake

    IPC分类号： H03J5/02 ,  H03J7/18 ,  H03J3/06

    CPC分类号： H03J1/0033 ,  H03J1/0091 ,  H03J3/06 ,  H03J5/0245

    摘要： A signal receiver generates a reference signal that sweeps frequencies of desired channel bands, and then feeds the reference signal to an input terminal of receiver unit via a signet-switching circuit that performs switching of the desired-channel signal and the reference signal. The signal receiver then detects the signal strength present in plural frequencies of intermediate frequencies delivered to an output terminal of the reference signal, and after storing detected signal data in a memory, the signal receiver compares the detected signal data to aimed frequency characteristics. Then, the signal receiver determines tuning voltages of respective tuning circuits so that difference arose from the comparison can be minimized. After determining the tuning voltages, these voltages are delivered to respective tuning circuits, and then switching operation between the reference signal and the desired channel signal is executed before the signal receiver eventually receives the switched signal.

    FINE GRAIN TUNING
    7.
    发明公开
    FINE GRAIN TUNING 有权
    细晶VOTE

    公开(公告)号：EP2454813A1

    公开(公告)日：2012-05-23

    申请号：EP10736659.3

    申请日：2010-07-16

    申请人： Cambridge Silicon Radio Limited

    发明人： CERCELARU, Sever

    IPC分类号： H03J3/06

    CPC分类号： H03J3/06

    摘要： A circuit tuneable between first and second frequencies comprising gain control circuitry operable to control the gain of the circuit between the first and second frequencies, the gain control circuitry comprising a resistor network having: at least two resistor lines arranged in parallel, each resistor line comprising one or more resistors; and for each resistor line, a switch operable to select or deselect the corresponding resistor line; the resistor lines and switches being arranged such that the net resistance of the resistor network is the parallel sum of each of the selected resistor lines; and logic circuitry configured to control said switches so as to minimise the variation in gain of the circuit between the first and second frequencies.