利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

497 条记录 (耗时 0.02 秒)

    STRUCTURE WITH DIFFERENTIAL AMPLIFIERS HAVING INPUT OFFSET AND RELATED METHODS
    1.
    发明公开
    STRUCTURE WITH DIFFERENTIAL AMPLIFIERS HAVING INPUT OFFSET AND RELATED METHODS 审中-公开

    公开(公告)号：EP4456424A1

    公开(公告)日：2024-10-30

    申请号：EP23203385.2

    申请日：2023-10-13

    申请人： GlobalFoundries Dresden Module One Limited Liability Company & Co. KG

    发明人： Stefanov, Stefan Manolov

    IPC分类号： H03K5/24 ,  G01R19/165

    摘要： Embodiments of the disclosure provide a structure with differential amplifiers (110, 112) each having an input offset, and related methods. A structure of the disclosure includes a first differential amplifier (110) coupled to an input line (114), a reference line (116), and a first output line (Out1). The first differential amplifier has a first input offset. A second differential amplifier (112) is coupled to the input line (114), the reference line (116) and to a second output line (Out2). The second differential amplifier has a second input offset in a different direction from the first input offset.

    COMPARATOR CIRCUIT, MISMATCH CORRECTION METHOD, AND MEMORY
    4.
    发明公开
    COMPARATOR CIRCUIT, MISMATCH CORRECTION METHOD, AND MEMORY 审中-公开

    公开(公告)号：EP4280461A1

    公开(公告)日：2023-11-22

    申请号：EP22757469.6

    申请日：2022-05-18

    申请人： Changxin Memory Technologies, Inc.

    发明人： TIAN, Kai ,  ZHU, Ling

    IPC分类号： H03K5/24

    摘要： The present disclosure relates to the field of semiconductor circuit design, and in particular, to a comparator circuit, a method for correcting mismatch and a memory. The comparator circuit includes a first transistor, a second transistor, a load unit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load unit is coupled to a second node, and another terminal of the load unit is coupled to the first control node and the second control node. The first adjustment circuit is configured to adjust, according to a first adjustment signal, a node potential of the first control node after the first transistor becomes conductive based on the first control signal. The second adjustment circuit is configured to adjust, according to a second adjustment signal, a node potential of the second control node after the second transistor becomes conductive based on the second control signal. The mismatch between the two input transistors of the differential structure is thus eliminated, thereby improving the memory performance.

    CASCADED MULTIPLE FEEDBACK CONTROLLER
    6.
    发明公开
    CASCADED MULTIPLE FEEDBACK CONTROLLER 审中-公开

    公开(公告)号：EP4131696A2

    公开(公告)日：2023-02-08

    申请号：EP22186080.2

    申请日：2022-07-20

    申请人： Hamilton Sundstrand Corporation

    发明人： IVES, Kyle Stephen ,  HARKE, Michael C. ,  SEAGREN, Robert L.

    IPC分类号： H02J1/08 ,  H02J1/10 ,  H02J1/14 ,  H03K5/24

    摘要： Systems for a cascaded multiple feedback generator controller are provided. Aspects include a direct current (DC) power supply comprising a generator (304) and a rectifier circuit (306) connected to a load, a first voltage sensing device coupled to a first point of regulation, a second voltage sensing device coupled to a second point of regulation, a generator controller (302) configured to receive a first voltage signal from the first voltage sensing device, receive a second voltage signal from the second voltage sensing device, determine an adjustment for the generator (304), the adjustment comprising a transient performance response and a voltage droop response, wherein the transient performance response is determined based on the first voltage signal, and wherein the voltage droop response is determined based on the second voltage signal, and operate the generator (304) based on the adjustment for the generator (304).

    MULTI-CHANNEL DIGITAL TO ANALOG CONVERTER
    8.
    发明公开
    MULTI-CHANNEL DIGITAL TO ANALOG CONVERTER 审中-公开

    公开(公告)号：EP4089925A1

    公开(公告)日：2022-11-16

    申请号：EP22168907.8

    申请日：2022-04-19

    申请人： NXP B.V.

    发明人： WANG, RuoXi ,  ZHANG, Hongyun ,  DUAN, XinDong

    IPC分类号： H03M1/66 ,  G01R19/00 ,  H03K5/24

    摘要： A multi-channel digital to analog converter, DAC, comprising: a DAC configured to provide an analog signal comprising a plurality of time division multiplexed sub-signals, each provided for one of a plurality of output channels; wherein each of the output channels include: a sampling capacitor; a selector switch configured to couple the sampling capacitor of the respective output channel to the output terminal of the DAC such that the sampling capacitor samples the analog signal over a plurality of discrete sampling periods; a comparator configured to provide a comparator output signal, wherein the sampling capacitor is coupled to an input terminal of the comparator; and an output control gate configured to control whether or not the comparator output signal is output from the respective output channel at a predetermined time later than a first of the respective plurality of discrete sampling periods.