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    COMBINED INPUT AND OUTPUT QUEUE FOR PACKET FORWARDING IN NETWORK DEVICES
    6.
    发明公开
    COMBINED INPUT AND OUTPUT QUEUE FOR PACKET FORWARDING IN NETWORK DEVICES 审中-公开

    公开(公告)号：EP4239976A2

    公开(公告)日：2023-09-06

    申请号：EP23183716.2

    申请日：2020-04-22

    Applicant: Juniper Networks, Inc.

    Inventor： FRINK, Craig R. ,  XU, Weidong ,  GUPTA, Anurag P. ,  AGASHE, Harshad B

    IPC: H04L49/90

    Abstract: An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue.

    PRIORITY QUEUE SORTING SYSTEM AND METHOD WITH DETERMINISTIC AND BOUNDED LATENCY
    8.
    发明公开
    PRIORITY QUEUE SORTING SYSTEM AND METHOD WITH DETERMINISTIC AND BOUNDED LATENCY 审中-公开

    公开(公告)号：EP4123992A1

    公开(公告)日：2023-01-25

    申请号：EP22185000.1

    申请日：2022-07-14

    Applicant: NXP B.V.

    Inventor： Deb, Abhijit Kumar ,  Pannell, Donald Robert ,  Gauthier, Claude Robert

    IPC: H04L49/901 ,  G06F15/80 ,  H04L49/90

    Abstract: A priority queue sorting system including a priority queue and a message storage. The priority queue includes multiple priority blocks that are cascaded in order from a lowest priority block to a highest priority block. Each priority block includes a register block storing an address and an identifier, compare circuitry that compares a new identifier with the stored identifier for determining relative priority, and select circuitry that determines whether to keep or shift and replace the stored address and identifier within the priority queue based on the relative priority. The message storage stores message payloads, each pointed to by a corresponding stored address of a corresponding priority block. Each priority block contains its own compare and select circuitry and determines a keep, shift, or store operation. Thus, sorting is independent of the length of the priority queue thereby achieving deterministic sorting latency that is independent of the queue length.

    METHOD AND SYSTEM FOR EFFECTIVE USE OF INTERNAL AND EXTERNAL MEMORY FOR PACKET BUFFERING WITHIN A NETWORK DEVICE
    9.
    发明公开
    METHOD AND SYSTEM FOR EFFECTIVE USE OF INTERNAL AND EXTERNAL MEMORY FOR PACKET BUFFERING WITHIN A NETWORK DEVICE 审中-公开

    公开(公告)号：EP4068732A1

    公开(公告)日：2022-10-05

    申请号：EP22162054.5

    申请日：2022-03-15

    Applicant: NXP USA, Inc.

    Inventor： St-Denis, Bernard Francois ,  Pillar, John ,  Lengacher, Allen

    IPC: H04L49/90

    Abstract: A mechanism is provided to maximize utilization of internal memory for packet queuing in network devices, while providing an effective use of both internal and external memory to achieve high performance, high buffering scalability, and minimizing power utilization. Embodiments initially store packet data received by the network device in queues supported by an internal memory. If internal memory utilization crosses a predetermined threshold, a background task performs memory reclamation by determining those queued packets that should be targeted for transfer to an external memory. Those selected queued packets are transferred to external memory and the internal memory is freed. Once the internal memory consumption drops below a threshold, the reclamation task stops.

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