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    ELECTRONIC APPARATUS AND OPERATION METHOD THEREOF
    7.
    发明公开
    ELECTRONIC APPARATUS AND OPERATION METHOD THEREOF 审中-实审

    公开(公告)号：EP4428681A1

    公开(公告)日：2024-09-11

    申请号：EP22916842.2

    申请日：2022-12-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： SHIN, Youngsang ,  KWAK, Jaehwan ,  KIM, Yuna ,  KIM, Taehyun ,  PARK, Hyuncheol ,  LEE, Namgwon ,  JE, Euijin ,  CHO, Yewon

    IPC分类号： G06F9/38 ,  G06F9/451 ,  G06F9/30 ,  G06N20/00

    CPC分类号： G06N20/00 ,  G06F9/30 ,  G06F9/451

    摘要： An operating method of an electronic device includes receiving a request to control of at least one application that is providable by the electronic device, obtaining second information according to a machine learning model based on first information corresponding to a history of use regarding the at least one application and at least one support element. The machine learning model predicts at least a probability of use of the at least one support element which supports execution of the at least one application based on the first information, and the method executes a function corresponding to the request to control the at least one application to be provided by the electronic device, based on the second information including at least the probability of use of the at least one support element which supports the execution of the at least one application.

    DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE
    9.
    发明公开
    DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE 审中-实审

    公开(公告)号：EP4425327A1

    公开(公告)日：2024-09-04

    申请号：EP23884011.0

    申请日：2023-02-27

    申请人： Hygon Information Technology Co., Ltd.

    发明人： CUI, Zehan

    IPC分类号： G06F9/38

    CPC分类号： Y02D10/00

    摘要： Embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device. The method comprises: generating an instruction fetch request carrying at least one switching mark, the switching mark at least indicating an instruction position for decoder group switching; in response to micro-ops obtained from decoding by decoder groups, acquiring an instruction stream fetched by means of the instruction fetch request, and according to the switching mark carried in the instruction fetch request, determining the instruction position for decoder group switching; according to the instruction position, distributing the instruction stream to multiple decoder groups for parallel decoding, and carrying a switching mark in a target micro-op obtained by decoding a target instruction, the target instruction being an instruction corresponding to the instruction position; and in response to searching a micro-op cache for micro-ops, if the instruction fetch request is hit in the micro-op cache, acquiring a corresponding micro-op from the micro-op cache. The embodiments of the present disclosure can improve the decoding performance of a processor.