利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.015 秒)

    Frequency multiplier
    1.
    发明公开
    Frequency multiplier 失效
    Frequenzvervielfacher。

    公开(公告)号：EP0521652A2

    公开(公告)日：1993-01-07

    申请号：EP92305845.7

    申请日：1992-06-25

    申请人： RAYTHEON COMPANY

    发明人： Russell, Mark E. ,  Pietrangelo, Gregory J. ,  Mara, John F., Jr. ,  Tipton, Michael C

    IPC分类号： H03B19/16

    CPC分类号： H03B19/18 ,  H03B19/00 ,  H03B19/16 ,  H03B2200/0028 ,  H03B2200/0088 ,  H03L5/00

    摘要： A frequency doubler (Fig. 7) or a frequency tripler (Fig. 4) is coupled to an amplifier (110) with a temperature compensation circuit (126) and a feed forward gain control loop (114,120,122,124,116). With such an arrangement, a frequency multiplier is provided wherein variations of an output signal of the frequency multiplier due to changing characteristics of the frequency multiplier caused by ambient temperature variation or from a varying input signal level are minimized. An anti-parallel pair of diodes (136a,136b) provides odd harmonics from an amplified (132) input RF signal. A high pass filter (138) selects the third harmonic and supplies it through an amplifier (112) and a coupler (114) to a variable attenuator (116). The coupler (114) supplies a signal to a detector (120) that drives one input of a differential amplifier (124). The temperature compensation circuit (126) supplies a reference signal to the other input of the differential amplifier (124). The output from the differential amplifier (124) is a control signal that controls the attenuator (116) to compensate for variations in the amplitude of the output from the high pass filter (138) and variation in the characteristics of the amplifiers (112,118) due to temperature change.

    摘要翻译： 倍频器（图7）或频率三倍（图4）通过温度补偿电路（126）和前馈增益控制回路（114,120,122,124,116）耦合到放大器（110）。 通过这种布置，提供了一种倍频器，其中由于由环境温度变化或变化的输入信号电平引起的倍频器特性的变化导致的倍频器的输出信号的变化被最小化。 反并联的二极管（136a，136b）从放大的（132）输入RF信号提供奇次谐波。 高通滤波器（138）选择三次谐波，并通过放大器（112）和耦合器（114）将其提供给可变衰减器（116）。 耦合器（114）向驱动差分放大器（124）的一个输入端的检测器（120）提供信号。 温度补偿电路（126）将参考信号提供给差分放大器（124）的另一个输入端。 来自差分放大器（124）的输出是控制信号，其控制衰减器（116）以补偿来自高通滤波器（138）的输出的幅度的变化和放大器（112,118）的特性的变化 到温度变化。

    ANALOGUE SYSTEM OF GENERATING QUADRATURE SIGNALS
    2.
    发明公开
    ANALOGUE SYSTEM OF GENERATING QUADRATURE SIGNALS 审中-公开
    模拟系统ZUR ERZEUGUNG VON QUADRATURSIGNALEN

    公开(公告)号：EP1469598A1

    公开(公告)日：2004-10-20

    申请号：EP01275063.4

    申请日：2001-12-20

    申请人： Universidad de Barcelona

    发明人： Lopez Villegas, José M. ,  Samitier i Marti, Josep ,  Cabanillas Costa, Josep

    IPC分类号： H03H7/19 ,  H03H11/18 ,  H03B27/00 ,  H03M5/16 ,  H03B19/03 ,  H03B19/16

    CPC分类号： H03B27/00 ,  H03B19/16 ,  H03H7/21 ,  H03H7/422 ,  H03H11/22 ,  H03J2200/38

    摘要： The invention relates to an analogue system of generating quadrature signals. The inventive system comprises: a) a first analogue frequency divider; and b) a second analogue frequency divider.Each of said dividers is supplied respectively with a d 1 and d 2 analogue signal having a frequency 2f, said signals (d 1 and d 2 ) being 180 ° phase shifted relative to each other. In this way, two analogue output quadrature signals s 1 and s 2 having frequency f are obtained at the output of each of the aforementioned frequency dividers, i. e. said signals are 90 ° phase shifted relative to each other. The aforementioned signals (d 1 and d 2 ) are obtained using a differential transformer (1). Moreover, each of the above-mentioned analogue frequency dividers can be formed, from the connection with the end of the auxiliary differential transformer (1), using an inverting transformer (2, 2a), two variable-capacity varactor diodes (3, 4, 3a, 4a), which are connected to the end of each of the windings of the inverting transformer (2, 2a), and a non-inverting transformer (5, 5a).

    摘要翻译： 本发明涉及产生正交信号的模拟系统。 本发明的系统包括：a）第一模拟分频器; 并且b）第二模拟分频器。每个所述分频器分别提供具有频率2f的d1和d2模拟信号，所述信号（d1和d2）相对于彼此相移180°。 以这种方式，在每个上述分频器i的输出端获得具有频率f的两个模拟输出正交信号s1和s2。 即 所述信号相对于彼此是90度相移。 使用差动变压器（1）获得上述信号（d1和d2）。 此外，上述模拟分频器中的每一个可以使用反相变压器（2,2a）从辅助差动变压器（1）的端部的连接形成，两个可变容量变容二极管（3,4） ，3a，4a），其连接到所述反相变压器（2,2a）的每个绕组的端部，以及非反相变压器（5,5a）。

    Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein
    3.
    发明公开
    Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein 失效
    一种频率合成器，用于产生高纯度的信号以及相关联的电路元件，例如VCO，PLL和信号发生器的发电机。

    公开(公告)号：EP0414260A2

    公开(公告)日：1991-02-27

    申请号：EP90116261.0

    申请日：1990-08-24

    申请人： ANRITSU CORPORATION

    发明人： Saeki Anritsu Okihara-Ryou, Hiroshi ,  Motoyama, Hatsuo

    IPC分类号： H03B21/01 ,  H03L7/087 ,  H03L7/099 ,  H03B19/16

    CPC分类号： H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    摘要： To output desired high purity signals, a frequency synthesizer was made to synthesize reference signals from a first and second signal generators (11, 12) in the same frequency band as a desired frequency band. Thereby, the resolution of the frequency synthesizer becomes twice the step ΔF. Also, the frequency synthe­sizer can interpolate the step size of the first signal generator with half the number of steps. While, heretofore, the 100-MHz step size was interpolated with Fq = 0, 10, 20, 30, 40 and 50 MHz, Fq = 0, 20, 40 MHz interpolation is made possible. This permits the syn­thesis of 580 MHz to 1280 MHz. In this case, however, the minimum difference between the sum and difference frequencies from the first and second signal generators (11, 12) is 40 MHz and the lowest frequency is 20 MHz. Thus, depending on mixer isolation, the spurious meas­ures become difficult. The frequency synthesizer of the present invention pays attention to the fact that 20 MHz step signals can be synthesized at frequencies which are integral multiples of Fq (multiples of 0 and 5 are excluded). When two-fold Fq is used, the minimum dif­ference between the sum and difference frequencies out­put from a mixer (13) is 80 MHz and the lowest used frequency is 40 MHz. The spurious measures by a PLL circuit (14) becomes easy. A frequency detector (18) forces the free-running frequency of a VCO included the PLL circuit. Control Data P and Q to the first and sec­ond signal generators are supplied from a control sec­tion (27) based on data Fi set by as frequency setting section (28).

    摘要翻译： 为了输出所需的高纯度的信号，这使得从在相同的频带作为一种期望的频率带的第一和第二信号发生器（11，12）合成的参考信号的频率合成器。 由此，频率合成器的分辨率变为两倍的步骤DELTA F.因此，频率合成器可以与步骤一半数量的内插所述第一信号发生器的步长大小。 而，迄今为止，在100-MHz的步长大小，其与Fq中= 0，10，20，30，40和50兆赫，F Q = 0，20，40 MHz的内插是可能的内插。 这允许580兆赫的合成，1280兆赫。 在这种情况下，然而，和与差之间的最小差值从所述第一和第二信号发生器频率（11，12）为40MHz，而最低频率为20MHz。 因此，根据混频器的隔离，寄生措施变得困难。 本发明的频率合成器注重可以在哪些是Fq上的整数倍的频率进行合成的factthat 20MHz的步骤信号（0和5的倍数除外）。 当使用两倍FQ，和与差之间的最小差值频率从混频器输出（13）是80MHz，最低使用频率为40兆赫。 由PLL电路（14）的寄生措施变得容易。 频率检测器（18）强制VCO的自由运行频率包括在PLL电路。 控制数据P和Q，以将第一和第二信号发生器，从一个控制部分（27），基于由设定为频率设定部（28）的数据网络连接提供。

    Transient discriminate harmonics generator
    5.
    发明公开
    Transient discriminate harmonics generator 失效
    Übergangssignalediskriminierender SignalgeneratorfürOberwellensignale。

    公开(公告)号：EP0629039A1

    公开(公告)日：1994-12-14

    申请号：EP94108698.5

    申请日：1994-06-07

    申请人： APHEX SYSTEMS, LTD.

    发明人： Werrbach, Donn

    IPC分类号： H03B19/16 ,  G10H1/16

    CPC分类号： H03B19/16 ,  G10H1/16 ,  G10H2230/271

    摘要： The present invention is a transient discriminate harmonics generator which receives an audio input signal and produces an output signal containing harmonics of the input signal. The output signal is amplitude shaped as a function of the input signal's time and amplitude envelope. The present invention transient discriminate harmonics generator generally comprises a control circuit for determining a control parameter, and a harmonics generating circuit regulated by the control circuit for producing an output signal containing harmonics of an input signal, where the transient discriminate harmonics generator first generates a relatively high level of harmonics at an initial occurrence of the input signal, then incrementally reduces the level of harmonics generated during a time period determined by the control parameter following the initial occurrence of the input signal, and finally produces a relatively low level of harmonics after the end of the time period.

    摘要翻译： 本发明是一种瞬态鉴别谐波发生器，其接收音频输入信号并产生包含输入信号的谐波的输出信号。 输出信号作为输入信号的时间和幅度包络的函数的幅度形状。 本发明的瞬态鉴别谐波发生器通常包括用于确定控制参数的控制电路和由控制电路调节的用于产生包含输入信号的谐波的输出信号的谐波发生电路，其中瞬态鉴别谐波发生器首先产生相对 在输入信号的初始出现时，高电平的谐波，然后递增地降低由在输入信号的初始出现之后由控制参数确定的时间段内产生的谐波电平，并且最终产生相对较低的谐波电平 时间段结束

    Frequency multiplier
    6.
    发明公开
    Frequency multiplier 失效
    频率乘法器

    公开(公告)号：EP0521652A3

    公开(公告)日：1993-06-16

    申请号：EP92305845.7

    申请日：1992-06-25

    申请人： RAYTHEON COMPANY

    发明人： Russell, Mark E. ,  Pietrangelo, Gregory J. ,  Mara, John F., Jr. ,  Tipton, Michael C

    IPC分类号： H03B19/16

    CPC分类号： H03B19/18 ,  H03B19/00 ,  H03B19/16 ,  H03B2200/0028 ,  H03B2200/0088 ,  H03L5/00

    摘要： A frequency doubler (Fig. 7) or a frequency tripler (Fig. 4) is coupled to an amplifier (110) with a temperature compensation circuit (126) and a feed forward gain control loop (114,120,122,124,116). With such an arrangement, a frequency multiplier is provided wherein variations of an output signal of the frequency multiplier due to changing characteristics of the frequency multiplier caused by ambient temperature variation or from a varying input signal level are minimized. An anti-parallel pair of diodes (136a,136b) provides odd harmonics from an amplified (132) input RF signal. A high pass filter (138) selects the third harmonic and supplies it through an amplifier (112) and a coupler (114) to a variable attenuator (116). The coupler (114) supplies a signal to a detector (120) that drives one input of a differential amplifier (124). The temperature compensation circuit (126) supplies a reference signal to the other input of the differential amplifier (124). The output from the differential amplifier (124) is a control signal that controls the attenuator (116) to compensate for variations in the amplitude of the output from the high pass filter (138) and variation in the characteristics of the amplifiers (112,118) due to temperature change.

    Schaltungsanordnung zur Erzeugung einer Taktfrequenz für ein Datenübertragungssystem
    9.
    发明公开
    Schaltungsanordnung zur Erzeugung einer Taktfrequenz für ein Datenübertragungssystem 无效
    用于产生时钟频率的数据传输系统的电路装置

    公开(公告)号：EP0774831A3

    公开(公告)日：1998-04-22

    申请号：EP96115256.8

    申请日：1996-09-24

    申请人： KE KOMMUNIKATIONS-ELEKTRONIK GMBH & CO

    发明人： Hennig, Andreas, Dipl.-Ing.

    IPC分类号： H03B19/16

    CPC分类号： H03B19/16

    摘要： Es wird eine Schaltungsanordnung zur Erzeugung einer Taktfrequenz für ein Datenübertragungssystem unter Verwendung eines spannungsgesteuerten Grundwellen-Quarzoszillators (VCXO) angegeben, dessen Frequenz in Abhängigkeit von der Steuerspannung in engen Grenzen veränderbar ist. Zur Verdoppelung der Frequenz des Grundwellen-Quarzoszillators (VCXO) ist dessen Ausgang (A) mit dem Eingang einer Gleichrichter-Brückenschaltung (1) verbunden, über deren Ausgang ein ohmscher Widerstand (2) liegt. An den ohmschen Widerstand (2) ist ein Komparator (3) mit seinen beiden Eingängen angeschlossen, an dessen Ausgang die Taktfrequenz (f) ansteht.