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10 条记录 (耗时 0.017 秒)

    A voltage controlled oscillator
    2.
    发明公开
    A voltage controlled oscillator 失效
    一个压控振荡器

    公开(公告)号：EP0583800A1

    公开(公告)日：1994-02-23

    申请号：EP93117167.2

    申请日：1990-08-24

    申请人： ANRITSU CORPORATION

    发明人： Saeki, Hiroshi, Anritsu Okihara-Ryou ,  Motoyama, Hatsuo

    IPC分类号： H03L7/099 ,  H03B5/12 ,  H03B21/01

    CPC分类号： H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    摘要： A voltage controlled oscillator is provided comprising resonant circuit means (301) and an active circuit means (303) having an active element T1, the input of the active circuit means being connected to the resonant circuit means (301). Variable capacitance ratio means (304) are connected to the active circuit means (303) in order to oscillate the active element T1 at a resonance frequency of the resonance circuit means (301). Variable control means are provided for changing the resonance frequency, so that the oscillator frequency of the active element T1 can be changed substantially linearly over a wide bandwidth, to thereby retain the amount of positive feed back at a predetermined level against the oscillator frequency of the active circuit means (303).

    摘要翻译： 提供一种压控振荡器，其包括谐振电路装置（301）和具有有源元件T1的有源电路装置（303），有源电路装置的输入连接到谐振电路装置（301）。 可变电容比装置（304）连接到有源电路装置（303），以便以谐振电路装置（301）的谐振频率振荡有源元件T1。 可变控制装置被设置用于改变谐振频率，使得有源元件T1的振荡器频率可以在宽带宽上基本线性地改变，从而将正反馈量保持在预定水平， 有源电路装置（303）。

    Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein
    6.
    发明公开
    Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein 失效
    一种频率合成器，用于产生高纯度的信号以及相关联的电路元件，例如VCO，PLL和信号发生器的发电机。

    公开(公告)号：EP0414260A2

    公开(公告)日：1991-02-27

    申请号：EP90116261.0

    申请日：1990-08-24

    申请人： ANRITSU CORPORATION

    发明人： Saeki Anritsu Okihara-Ryou, Hiroshi ,  Motoyama, Hatsuo

    IPC分类号： H03B21/01 ,  H03L7/087 ,  H03L7/099 ,  H03B19/16

    CPC分类号： H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    摘要： To output desired high purity signals, a frequency synthesizer was made to synthesize reference signals from a first and second signal generators (11, 12) in the same frequency band as a desired frequency band. Thereby, the resolution of the frequency synthesizer becomes twice the step ΔF. Also, the frequency synthe­sizer can interpolate the step size of the first signal generator with half the number of steps. While, heretofore, the 100-MHz step size was interpolated with Fq = 0, 10, 20, 30, 40 and 50 MHz, Fq = 0, 20, 40 MHz interpolation is made possible. This permits the syn­thesis of 580 MHz to 1280 MHz. In this case, however, the minimum difference between the sum and difference frequencies from the first and second signal generators (11, 12) is 40 MHz and the lowest frequency is 20 MHz. Thus, depending on mixer isolation, the spurious meas­ures become difficult. The frequency synthesizer of the present invention pays attention to the fact that 20 MHz step signals can be synthesized at frequencies which are integral multiples of Fq (multiples of 0 and 5 are excluded). When two-fold Fq is used, the minimum dif­ference between the sum and difference frequencies out­put from a mixer (13) is 80 MHz and the lowest used frequency is 40 MHz. The spurious measures by a PLL circuit (14) becomes easy. A frequency detector (18) forces the free-running frequency of a VCO included the PLL circuit. Control Data P and Q to the first and sec­ond signal generators are supplied from a control sec­tion (27) based on data Fi set by as frequency setting section (28).

    摘要翻译： 为了输出所需的高纯度的信号，这使得从在相同的频带作为一种期望的频率带的第一和第二信号发生器（11，12）合成的参考信号的频率合成器。 由此，频率合成器的分辨率变为两倍的步骤DELTA F.因此，频率合成器可以与步骤一半数量的内插所述第一信号发生器的步长大小。 而，迄今为止，在100-MHz的步长大小，其与Fq中= 0，10，20，30，40和50兆赫，F Q = 0，20，40 MHz的内插是可能的内插。 这允许580兆赫的合成，1280兆赫。 在这种情况下，然而，和与差之间的最小差值从所述第一和第二信号发生器频率（11，12）为40MHz，而最低频率为20MHz。 因此，根据混频器的隔离，寄生措施变得困难。 本发明的频率合成器注重可以在哪些是Fq上的整数倍的频率进行合成的factthat 20MHz的步骤信号（0和5的倍数除外）。 当使用两倍FQ，和与差之间的最小差值频率从混频器输出（13）是80MHz，最低使用频率为40兆赫。 由PLL电路（14）的寄生措施变得容易。 频率检测器（18）强制VCO的自由运行频率包括在PLL电路。 控制数据P和Q，以将第一和第二信号发生器，从一个控制部分（27），基于由设定为频率设定部（28）的数据网络连接提供。

    A phase locked loop circuit
    8.
    发明公开
    A phase locked loop circuit 失效
    锁相环电路

    公开(公告)号：EP0583804A1

    公开(公告)日：1994-02-23

    申请号：EP93117197.9

    申请日：1990-08-24

    申请人： ANRITSU CORPORATION

    发明人： Saeki, Hiroshi, Anritsu Okihara-Ryou ,  Motoyama, Hatsuo

    IPC分类号： H03L7/093 ,  H03L7/113 ,  H03B21/01

    CPC分类号： H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    摘要： A phase locked loop circuit is provided comprising a voltage controlled oscillator (221) capable of outputting a variable oscillation frequency signal. A phase detector (222) compares the output signal of the voltage control oscillator (221) with a reference signal and outputs an error signal. An integrator (223) integrates the error signal and extracts a direct current variable component which is fed by a loop filter (224) from the integrator (223) to the voltage controlled oscillator (221) as a control signal. An alternate current coupling circuit (230) is provided for adding only an alternate current component contained in the output error signal to the control signal for feeding same to the voltage controlled oscillator (221). A compensating circuit (231) is inserted in the signal path of the alternate current coupling circuit (230), the compensating circuit (231) having a cut-off frequency exceeding the cut-off frequency of the integrator (223).

    摘要翻译： 提供一种锁相环电路，其包括能够输出可变振荡频率信号的压控振荡器（221）。 相位检测器（222）将压控振荡器（221）的输出信号与参考信号进行比较并输出误差信号。 积分器（223）对误差信号进行积分并提取由积分器（223）的环路滤波器（224）馈送到电压控制振荡器（221）的直流电流可变分量作为控制信号。 提供交流耦合电路（230），用于仅将包含在输出误差信号中的交流分量加到控制信号上，以将其馈送到压控振荡器（221）。 补偿电路（231）插入交流耦合电路（230）的信号路径中，补偿电路（231）的截止频率超过积分器（223）的截止频率。

    A phase locked loop circuit including a frequency detection function
    9.
    发明公开
    A phase locked loop circuit including a frequency detection function 失效
    用频率检测锁相环电路装置。

    公开(公告)号：EP0583801A1

    公开(公告)日：1994-02-23

    申请号：EP93117172.2

    申请日：1990-08-24

    申请人： ANRITSU CORPORATION

    发明人： Saeki, Hiroshi, Anritsu Okihara-Ryou ,  Motoyama, Hatsuo

    IPC分类号： H03L7/113 ,  H03B21/01

    CPC分类号： H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    摘要： A phase locked loop circuit is provided comprising a voltage controlled oscillator (17) and a phase detector (15) for detecting a phase difference and outputting a corresponding error voltage. A loop filter (16) integrates the error voltage and controls the voltage controlled oscillator (17). A first frequency comparator (23) is provided for dividing the frequency of the output signal of the voltage controlled oscillator (17) according to an upper limit frequency supplied by a control section (27). The comparator (23) compares frequencies of a reference signal and the frequency-divided signal and outputs down-pulses when the frequency of the frequency-divided signal is higher than that of the reference signal. Similarly, a second frequency comparator (24) divides and compares the output signal of the voltage controlled oscillator (17) with a second reference signal and outputs an up-pulse when the frequency of the divided signal is lower than the second reference signal. Further provided is an up-down processor (25) for supplying the up-pulses and the down-pulses to the loop filter (16) to add to the error voltage from the phase detector (15).

    Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein
    10.
    发明公开
    Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein 失效
    用于实现高纯度信号和电路设备的发生器的频率合成器，如VCO，PLL和SG，使用的

    公开(公告)号：EP0414260A3

    公开(公告)日：1992-08-26

    申请号：EP90116261.0

    申请日：1990-08-24

    申请人： ANRITSU CORPORATION

    发明人： Saeki Anritsu Okihara-Ryou, Hiroshi ,  Motoyama, Hatsuo

    IPC分类号： H03B21/01 ,  H03L7/087 ,  H03L7/099 ,  H03B19/16

    CPC分类号： H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    摘要： To output desired high purity signals, a frequency synthesizer was made to synthesize reference signals from a first and second signal generators (11, 12) in the same frequency band as a desired frequency band. Thereby, the resolution of the frequency synthesizer becomes twice the step ΔF. Also, the frequency synthe­sizer can interpolate the step size of the first signal generator with half the number of steps. While, heretofore, the 100-MHz step size was interpolated with Fq = 0, 10, 20, 30, 40 and 50 MHz, Fq = 0, 20, 40 MHz interpolation is made possible. This permits the syn­thesis of 580 MHz to 1280 MHz. In this case, however, the minimum difference between the sum and difference frequencies from the first and second signal generators (11, 12) is 40 MHz and the lowest frequency is 20 MHz. Thus, depending on mixer isolation, the spurious meas­ures become difficult. The frequency synthesizer of the present invention pays attention to the fact that 20 MHz step signals can be synthesized at frequencies which are integral multiples of Fq (multiples of 0 and 5 are excluded). When two-fold Fq is used, the minimum dif­ference between the sum and difference frequencies out­put from a mixer (13) is 80 MHz and the lowest used frequency is 40 MHz. The spurious measures by a PLL circuit (14) becomes easy. A frequency detector (18) forces the free-running frequency of a VCO included the PLL circuit. Control Data P and Q to the first and sec­ond signal generators are supplied from a control sec­tion (27) based on data Fi set by as frequency setting section (28).