公开(公告)号：EP4485803A1

公开(公告)日：2025-01-01

申请号：EP24182467.1

申请日：2024-06-17

Applicant: Avago Technologies International Sales Pte. Limited

Inventor： He, Tim ,  Fallahi, Siavash ,  Huang, Zhi ,  Nazemi, Ali ,  Cao, Jun

IPC: H03L7/00 ,  H03B27/00

Abstract: A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.

公开(公告)号：EP4211802A1

公开(公告)日：2023-07-19

申请号：EP21773789.9

申请日：2021-09-10

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： BURKHARDT, Frank ,  LIPP, Stefan ,  SCHUH, Kirsten ,  JUÁREZ PEÑA, Jorge Luiz ,  SKUBICH, Christian ,  PETER, Nico ,  HUPP, Jürgen ,  WINDISCH, Thomas

IPC: H03L1/00 ,  H03L7/00

公开(公告)号：EP4181454A1

公开(公告)日：2023-05-17

申请号：EP22207007.0

申请日：2022-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Juyun ,  KIM, Sunggeun ,  LEE, Hyeonju ,  SON, Seuk ,  KIM, Kangjik ,  PARK, Jaehyun

IPC: H04L7/00 ,  H03L7/00

Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.

公开(公告)号：EP4113839A1

公开(公告)日：2023-01-04

申请号：EP22180530.2

申请日：2022-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehong JUNG, Jaehong ,  OH, Seunghyun ,  LEE, Jinhyeon ,  HA, Gihyeok ,  KIM, Seungjin ,  KIM, Joomyoung ,  YOUN, Yelim ,  LEE, Jaehoon

IPC: H03K3/02 ,  H03K3/0231 ,  H03L7/00

Abstract: A clock integrated circuit (100) is provided. The clock integrated circuit includes: a first clock generator (110) which includes a crystal oscillator (XTAL) configured to generate a first clock signal (fxo); and a second clock generator (120) which includes a resistance-capacitance (RC) oscillator (121) and a first frequency divider (122), and is configured to: generate a second clock signal (f RTC )using the first frequency divider (122) based on a clock signal (f RCO ) output from the RC oscillator (121); perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider (122) to a first frequency division ratio based on the first clock signal (fxo) ; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

公开(公告)号：EP3691374B1

公开(公告)日：2022-02-16

申请号：EP18862205.4

申请日：2018-09-30

Inventor： LI, Chao ,  FENG, Shulan ,  WANG, Junwei ,  WEI, Jingxin ,  FAN, Weiwei ,  ZHU, Jun ,  JIA, Qiong ,  LUO, Jun

IPC: H04W72/04 ,  H04L5/00 ,  H03L7/00

公开(公告)号：EP3837770A1

公开(公告)日：2021-06-23

申请号：EP19830698.7

申请日：2019-06-25

Applicant: BAE SYSTEMS Information and Electronic Systems Integration, Inc.

Inventor： JANSEN, Douglas S.

IPC: H03L7/07 ,  H03B25/00 ,  H03L7/00 ,  H03L7/06

公开(公告)号：EP3260881B1

公开(公告)日：2021-04-21

申请号：EP15882622.2

申请日：2015-02-19

Inventor： KURASHIGE, Kazunori

IPC: G01S13/34 ,  H03L7/00 ,  G01S7/35 ,  G01S7/40 ,  G06F1/03 ,  H03M1/10 ,  H03L1/02 ,  G01S13/58 ,  G01S13/93 ,  H03M1/66

公开(公告)号：EP3701632A1

公开(公告)日：2020-09-02

申请号：EP19765962.6

申请日：2019-07-03

Applicant: Shenzhen Goodix Technology Co., Ltd.

Inventor： EMIRA, Ahmed ,  HUSSIEN, Faisal

IPC: H04B1/04 ,  H03L7/00

公开(公告)号：EP2533456B1

公开(公告)日：2020-04-01

申请号：EP12182848.7

申请日：2006-07-19

Applicant: ATI Technologies ULC

Inventor： Lee, Edward ,  Bomdica, Arvind ,  Chen, Lin ,  Gauthier, Claude ,  Huynh, Sam ,  Ng, Hiok-Tiaq ,  Ling, John ,  Ho, Jennifer ,  M.K, Siji ,  Yee, Gin ,  Macri, Joseph

IPC: H04L7/033 ,  H03L7/00

公开(公告)号：EP3549263A1

公开(公告)日：2019-10-09

申请号：EP17883350.5

申请日：2017-12-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： GU, Liang ,  CAO, Yuming ,  DANG, Yen ,  LEI, Gong ,  GU, Yifan ,  LEE, Hung-Yi ,  DESHPANDE, Mamatha ,  SHIH, Shou-Po ,  LIU, Miao ,  LEI, Gong

IPC: H03L7/00