MULTI-ELEMENT SENSOR DEVICE AND SIGNAL PROCESSING METHOD

    公开(公告)号:JPH09322066A

    公开(公告)日:1997-12-12

    申请号:JP13311796

    申请日:1996-05-28

    申请人: FUJITSU LTD

    IPC分类号: H04N5/33 H03K5/125 H03M1/12

    摘要: PROBLEM TO BE SOLVED: To provide a multi-element sensor device and a signal processing method capable of reducing noise due to the distortion of output signals and highly accurately detecting image signals even in a system using a multi-element sensor such as a multi-element type infrared sensor or the like by providing a waveform shaping circuit. SOLUTION: In this multi-element sensor device provided with the multi- element sensor 1 and a signal processing circuit 2 for processing the output signals from the multi-element sensor 1, the waveform shaping circuit 3 for shaping the waveform of the output signals of the multi-element sensor 1 is provided. The waveform shaping circuit 3 is controlled by a timing pulse generation circuit 7, converts the output signals of the multi-element sensor 1 of the distorted waveform to rectangular waves and outputs them to a sample-and-hold circuit 8. Thus, dispersion is eliminated from an output voltage after sampling and holding by the sample-and-hold circuit 8 and the multi-element sensor device capable of reducing the noise due to the distortion of the output signals is obtained.

    WAVEFORM SHAPING CIRCUIT FOR CLOCK SIGNAL

    公开(公告)号:JPH09321588A

    公开(公告)日:1997-12-12

    申请号:JP13037896

    申请日:1996-05-24

    申请人: SHARP KK

    发明人: KITANO SABURO

    摘要: PROBLEM TO BE SOLVED: To provide a waveform shaping circuit for a clock signal in which electromagnetic noise radiated from a signal line is reduced, through which the clock signal is supplied. SOLUTION: A clock signal being a pulse signal outputted from an output terminal 32 of a clock signal output IC is given to a series resonance circuit consisting of an inductive element 22, a capacitive element 23 and an input capacitor 37 of a waveform shaping circuit 21, in which the signal is converted into a sine wave in which harmonic components are limited. Furthermore, the amplitude of the sine wave depends on the sets of capacitance C2, C1 of the capacitive element 23 and the input capacitor 37, and the DC voltage level of the sine wave depends on the sets of resistance values R2, R1 of a resistive element 24 and an input resistor 36.

    BURST LIGHT RECEPTION CIRCUIT
    84.
    发明专利

    公开(公告)号:JPH098739A

    公开(公告)日:1997-01-10

    申请号:JP14893195

    申请日:1995-06-15

    申请人: HITACHI LTD

    摘要: PURPOSE: To exactly perform the pulse reproduction of burst light by setting an optimum threshold voltage without depending on the fluctuation of a light reception level and the change of an input signal pattern. CONSTITUTION: An input signal and a reference potential are added by an adder 1 and inputted to a comparator 6. An adder 2 adds the reference potential and the input signal as well. The output of the adder 2 is inputted through a low-pass filter 5 to the comparator 6 as the threshold voltage. Since the level of the input signal to be superimposed on the reference input side of the comparator is controlled by the adders 1 and 2, the threshold voltage not depending on the fluctuation of a light reception level and the change in the pattern of the input signal can be set and the pulse of burst light can be exactly reproduced.

    WAVEFORM SHAPING CIRCUIT FOR DIGITAL DATA

    公开(公告)号:JPH08172345A

    公开(公告)日:1996-07-02

    申请号:JP34116894

    申请日:1994-12-19

    发明人: ANDO KAORU

    摘要: PURPOSE: To make it possible to reduce the influence of noise without executing adjustment by removing data not meeting standard requirements as a noise component or adjusting pulse width to obtain serial data meeting the standard requirements. CONSTITUTION: An oscillation part 1 generates a clock to be a reference for waveform shaping and noise removal. A noise removing part 2 is constituted of a shift register or the like, removes received data =2/5 the pulse wide standard and one-clock variation exists on the way, the data are corrected so as to be continued to remove interruption due to the noise. Each of pulse detection parts 3 to 5 constituted of counters or the like detects a pulse with previously determined pulse width from digital data outputted from the noise removing part 2 and a data shaping part 6 shapes the waveform of input data to digital data with previously determined pulse width.

    WAVEFORM SHAPING CIRCUIT
    86.
    发明专利

    公开(公告)号:JPH07193474A

    公开(公告)日:1995-07-28

    申请号:JP33251093

    申请日:1993-12-27

    申请人: SHARP KK

    发明人: MASUDA YOSHIFUMI

    IPC分类号: H03K5/125 H03K5/08

    摘要: PURPOSE:To shape a waveform by generating a stable comparison signal while using a voltage with an input voltage used as a reference as a comparing voltage. CONSTITUTION:A select signal output means 2 is turned on and off corresponding to an output from a differential amplifier 3. Based on an input voltage VB, a comparison voltage setting means 1 sets a comparison voltage VC. The voltage VC is delayed to rise or fall of the input voltage VB because of the response characteristics of a photodetector, the threshold voltages of respective transistors inside the waveform forming circuit and the transient characteristics of switching or the like. Thus, when an input signal B is changed, the voltage VB of the input signal crosses the comparison voltage VC. The rise and fall of the input voltage VB are detected by utilizing this crossing of respective voltages VB and VC caused by the delay inside the circuit.

    BUS DRIVER CIRCUIT
    87.
    发明专利

    公开(公告)号:JPH07115439A

    公开(公告)日:1995-05-02

    申请号:JP28190493

    申请日:1993-10-16

    申请人: NEC CORP

    发明人: KAMIYA HIROSHI

    摘要: PURPOSE:To provide the bus driver circuit which selects an optimum through rate where efficient transmission is performed at a high speed. CONSTITUTION:First to N-th MOS transistors TRs 10(1) to 10(N) connected in series between the waveform input terminal and the waveform output terminal and first to M-th control MOS TRs 11(1) to 11(M) are provided. Sources of first to M-th MOS TRs are connected to drains of first to M-th control MOS TRs. Gates of (M+1)th to N-th MOS TRs are connected to a ground 30, and gates of first to M-th control MOS TRs are connected to control signals 81(1) to 81(M) which turn on/off first to M-th control MOS TRs. The source of each control MOS TR is connected to the ground through first to M-th resistors. Thus, the optimum through rate is selected in accordance with the classification and the the property of the waveform, the transmission speed, etc.

    PHOTOELECTRIC CURRENT FREQUENCY CONVERTING CIRCUIT

    公开(公告)号:JPH06308585A

    公开(公告)日:1994-11-04

    申请号:JP10119793

    申请日:1993-04-27

    申请人: NIKON CORP

    发明人: SAKAMOTO HIROSHI

    IPC分类号: G03B15/05 H03K5/125 H05B41/32

    摘要: PURPOSE:To replace photometry processing executed in an analog system with the digital processing of a microcomputer, etc., and to make the total circuit scale small by forming the number of pulses in proportion to a photoelectric current from a light receiving element, counting the pulses and detecting a emitted light quantity. CONSTITUTION:When a light emission starting signal is outputted from a sequence control circuit 8 to a light emission control circuit 2, flashing is started and a light receiving circuit 3 converts the reflected light of an object in the flashing of the light emitting part 1 into the photoelectric current, in external automatic light control. Then, a photoelectric current-frequency converting circuit 4 is a circuit generating a frequency in accordance with the photoelectric current generated by the light receiving circuit 3 and counts the outputted frequency by a counter 5. The output of the counter 5 is compared with that of a reference value setting means 7 by a comparing circuit 6 and when the output of the counter 5 coincides with that of the means 7 or is larger than that, a light emission stopping signal is outputted to the light emission control circuit 2 from the comparing circuit 6 and the flashing is completed.

    CIRCUIT REDUCING UNDERSHOOT
    89.
    发明专利

    公开(公告)号:JPH05175798A

    公开(公告)日:1993-07-13

    申请号:JP30271791

    申请日:1991-10-23

    申请人: MOTOROLA INC

    IPC分类号: H03K5/125 H03K17/16

    摘要: PURPOSE: To provide a circuit for reducing negative ground bounce in respect to the ground reference of CMOS circuit and a circuit for reducing the peak of negative undershoot in respect to the ground reference of CMOS circuit when transiting the CMOS circuit from logical high to logical low. CONSTITUTION: This circuit having an input terminal 24 and an output terminal 26 for reducing the negative ground bounce in respect to the ground reference of CMOS circuit is provided with an output buffer 22, and that output buffer 22 has an input to be coupled with the input terminal of circuit and an output to be coupled with the output terminal of circuit. A NOR gate 28 has 1st and 2nd inputs and these inputs are respectively coupled with the input terminal and output terminal of circuit. Injection circuits 32 and 34 are coupled with the output of NOR gate and the input terminal of circuit and supply a predetermined current to the output terminal of circuit.

    SEMICONDUCTOR INTEGRATED CIRCUIT
    90.
    发明专利

    公开(公告)号:JPH04258014A

    公开(公告)日:1992-09-14

    申请号:JP1888291

    申请日:1991-02-12

    发明人: KAWAMOTO SATORU

    IPC分类号: G11C11/409 H03K5/01 H03K5/125

    摘要: PURPOSE:To improve the operating speed of a succeeding circuit by improving an unsharpened transmission signal waveform of a long distance wiring part with respect to a waveform shaping circuit improving the unsharpened transmission signal waveform due to a parasitic resistance or a parasitic capacitance of the long distance wiring part. CONSTITUTION:A waveform shaping circuit 11 to improve the rising or falling speed of a pulse signal SG sent through a signal wire 2 by means of feedback action is connected between an output buffer circuit 1 and an input buffer circuit 3, and the feedback action of the waveform shaping circuit 11 is controlled by using a control signal SGC synchronously with the pulse signal SG so that the feedback action does not give effect onto a load of the output buffer circuit 1.