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    High-speed switching low noise charge pump
    4.
    发明专利
    High-speed switching low noise charge pump 有权

    公开(公告)号：JP2011504051A

    公开(公告)日：2011-01-27

    申请号：JP2010534148

    申请日：2008-11-12

    Applicant: クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： ヤン、ジョンシク ,  リー、サン・オー ,  ワン、シェン

    IPC: H03L7/093

    CPC classification number: H03L7/0896 ,  H03L7/18

    Abstract: 本発明のある実施形態において、チャージポンプの方法が開示されている。 その方法は、複数のトランジスタをバイアスすることと、バイアストランジスタを通して出力端子で正味電荷を加えたり除去したりするためにペアのメイントランジスタスイッチを切り換えることと、メイントランジスタスイッチがオフにされる時、補助トランジスタスイッチをオンにすることとを含む。 補助トランジスタスイッチは、オンの時、メイントランジスタスイッチとバイアストランジスタとの間のノードに補助等化経路を提供する。 補助等化経路は、バイアストランジスタを急速にオフにするため、及び、チャージポンプの出力端子のノイズを削減するために、中間ノード同士の電圧を均等化する。
    【選択図】図２

    Integrated voltage-controlled oscillator circuit
    7.
    发明专利
    Integrated voltage-controlled oscillator circuit 有权

    公开(公告)号：JP2012517158A

    公开(公告)日：2012-07-26

    申请号：JP2011548411

    申请日：2010-02-02

    Applicant: クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： チャウラ、ビプル ,  ワン、シェン

    IPC: H03B5/12 ,  H03B5/02 ,  H04B1/40

    CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1218 ,  H03B5/1243 ,  H03B5/1296

    Abstract: Techniques for providing voltage-controlled oscillator circuits having improved phase noise performance and lower power consumption. In an exemplary embodiment, a voltage controlled oscillator (VCO) is coupled to a mixer or a frequency divider such as a divide-by-two circuit. The VCO includes a transistor pair with magnetically cross-coupled inductors, and variable capacitance coupled to the gates of the transistor pair. In an exemplary embodiment, a frequency divider is configured to divide the frequency of the differential current flowing through the transistor pair to generate the LO output. In an alternative exemplary embodiment, a mixer is configured to mix the differential current flowing through the transistor pair with another signal. The VCO and mixer or frequency divider share common bias currents, thereby reducing power consumption. Various exemplary apparatuses and methods utilizing these techniques are disclosed.

    Fast divide - by - two circuit
    9.
    发明专利
    Fast divide - by - two circuit 有权

    公开(公告)号：JP2012532517A

    公开(公告)日：2012-12-13

    申请号：JP2012517928

    申请日：2010-07-02

    Applicant: クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： チャン、ナガー・ロン・アラン ,  ワン、シェン

    IPC: H03K27/00 ,  H03K3/356 ,  H03K5/00

    CPC classification number: H03K3/35613

    Abstract: A high frequency divider involves a plurality of differential latches. Each latch includes a pair of cross-coupled P-channel transistors and a variable resistance element. The latch is controlled to have a lower output resistance at high operating frequencies by setting a multi-bit digital control value supplied to the variable resistance element. Controlling the latch to have a reduced output resistance at high frequencies allows the 3 dB bandwidth of the latch to be maintained over a wide operating frequency range. The variable resistance element is disposed between the two differential output nodes of the latch such that appreciable DC bias current does not flow across the variable resistance element. As a consequence, good output signal voltage swing is maintained at high frequencies, and divider current consumption does not increase appreciably at high frequencies as compared to output signal swing degradation and current consumption increases in a conventional differential latch divider.

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