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16 条记录 (耗时 0.016 秒)

    PASSBOOK PRINTER
    4.
    发明专利
    PASSBOOK PRINTER 失效

    公开(公告)号：JPH03227268A

    公开(公告)日：1991-10-08

    申请号：JP2184190

    申请日：1990-01-31

    申请人： KOFU NIPPON DENKI KK

    发明人： ENDO HIROYUKI

    IPC分类号： B41J3/32 ,  B41J3/54

    摘要： PURPOSE:To make it possible to respectively perform printing for a normal passbook and printing by Braille points for a Braille points passbook by controlling the title printer in such a manner that printing is performed by one printing device between a printing device and printing device for Braille points, in response to an identification result by an identification device. CONSTITUTION:When a passbook is taken up by a take-up/discharge mechanism 2, a mark which is applied on the passbook is identified by the take-up/discharge mechanism 2, and to be a normal passbook or passbook for Braille points is discriminated. Then, the passbook is carried to a printing mechanism 4 by a carrying mechanism 3, and is printed by the printing mechanism 4 with control by a control unit 1. That is, the control unit 1 controls the printing mechanism 4 to perform normal printing when the passbook is a normal passbook, and controls the printing mechanism 4 to perform printing for Braille points, i.e., to give fine protrusions from the rear side of the passbook by pressing in order to indicate letters and numbers, when the passbook is a passbook for Braille points. When printing for the passbook is completed at the printing mechanism 4, the passbook is carried again to the take-up/discharge mechanism 2 through the carrying mechanism 3, and is discharged to the outside from the take-up/discharge mechanism 2.

    DECODE CIRCUIT, DECODE METHOD AND TIMING PULSE GENERATING CIRCUIT
    5.
    发明专利
    DECODE CIRCUIT, DECODE METHOD AND TIMING PULSE GENERATING CIRCUIT 失效

    公开(公告)号：JP2002043901A

    公开(公告)日：2002-02-08

    申请号：JP2000221228

    申请日：2000-07-21

    申请人： MIYAGI NIPPON DENKI KK

    发明人： ENDO HIROYUKI

    IPC分类号： G06F1/06 ,  G06F1/12 ,  H03K5/1252

    摘要： PROBLEM TO BE SOLVED: To overcome the problem such that a conventional decode circuit used for a timing pulse generating circuit or the like and consisting of a combination of logic gates such as AND and OR gates, has caused excess power consumption in the case of CMOS process devices due to an output change resulting from a delay time difference of signals given to the OR gates or the like, that is, hazard. SOLUTION: The decode circuit of this invention is a decode circuit provided with at least one n-input logic gate (n is an integer of 3 or over) and one of n-sets of input signals is a clock signal. The clock signal is given to the n-input logic gate earlier than the other data signals in terms of time. The logic gate is an OR gate or a NAND gate. This decode circuit causes no hazard because the clock signal masks factors causing the hazard.

    CLOCK TRANSFER CIRCUIT
    6.
    发明专利
    CLOCK TRANSFER CIRCUIT 失效

    公开(公告)号：JP2000269940A

    公开(公告)日：2000-09-29

    申请号：JP6930599

    申请日：1999-03-15

    申请人： MIYAGI NIPPON DENKI KK

    发明人： ENDO HIROYUKI

    IPC分类号： H04L7/00

    摘要： PROBLEM TO BE SOLVED: To obtain a clock transfer circuit that can distribute gap parts included in received data and provide an output of resulting data with minimized gap parts. SOLUTION: Since a memory 10 writes data by using a write address WR initialized for each frame by an input frame pulse, and the data are read therefrom by using a read address RD initialized for each frame with a delayed frame pulse from a delay section 13, propagation of gap parts of data by phase comparison is eliminated, and the read sequence by using read addresses is devised to distribute the gap parts, thereby distributing and minimizing the gap parts included in received data.

    SAVING AND RESTORING SYSTEM FOR ARBITRARY REGISTER
    7.
    发明专利
    SAVING AND RESTORING SYSTEM FOR ARBITRARY REGISTER 失效

    公开(公告)号：JPH02100142A

    公开(公告)日：1990-04-12

    申请号：JP25296988

    申请日：1988-10-07

    申请人： NEC CORP ,  KOFU NIPPON DENKI KK

    发明人： MURATA MASAHIRO ,  ENDO HIROYUKI

    IPC分类号： G06F9/46 ,  G06F9/48

    摘要： PURPOSE:To execute the saving and the restoring of an arbitrary register by a single instruction, respectively, and also, to reduce an overhead of the saving and the restoring of the register by registering in advance the register to be brought to saving in a command register. CONSTITUTION:At the time of bringing an arbitrary register to saving, an instruction for storing a value in a command register 14 and an instruction for bringing the arbitrary register to saving are incorporated in a ROM 11. When a bit of the command register 14 is '1', the corresponding register is brought to saving and restoring by arbitrary register saving and restoring instructions. When the bi of the command register 14 is '0', the corresponding register is not brought to saving and restoring by the arbitrary saving and restoring instructions. In such a manner, the saving and the restoring of the arbitrary register are executed by a single instruction, and the overhead of the saving and the restoring of the register can be reduced.

    CLOCK RELOADING CIRCUIT
    8.
    发明专利
    CLOCK RELOADING CIRCUIT 失效

    公开(公告)号：JP2000269941A

    公开(公告)日：2000-09-29

    申请号：JP6930699

    申请日：1999-03-15

    申请人： MIYAGI NIPPON DENKI KK

    发明人： ENDO HIROYUKI

    IPC分类号： H04L7/00

    摘要： PROBLEM TO BE SOLVED: To easily avoid a slip without changing the readout order of readout addresses by writing input data to a storage means according to write addresses, reading the input data out according to the readout addresses, alternately placing read and write means in operation, and selecting and outputting input data read out by a read and write means in operation. SOLUTION: Memories 10-1 and 10-2 of systems 1 and 2 are placed in operation by turns, in with of frames, by using input frame pulses and the memory 10-1 of the system 1 are placed in writing and reading operation by a choice 1 and a choice 2 for the 1st frame of input data. By using different memories for each frame, both the write and read addresses overlap with each other, even at the place where the reading of a last frame as a slip occurrence place and the writing of a next frame overlap with each other, so that a slip can be avoided without varying a WR-RD address initial phase difference and the memory capacity and changing the readout order of RD addresses.