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1.Computer system architecture for a processor connected to a high speed bus transceiver 有权
Title translation: 用于连接到高速总线收发器的处理器的计算机系统架构公开(公告)号:US07234017B2
公开(公告)日:2007-06-19
申请号:US11064745
申请日:2005-02-24
Applicant: Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
Inventor: Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC: G06F13/36
CPC classification number: G06F13/4059
Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
Abstract translation: 高速计算机处理器系统具有用于图形处理器的高速接口。 优选实施例将来自国际商业机器公司(IBM)的称为Giga-Processor Ultralite(GPUL)110的PowerPC微处理器与多芯片模块上的高速接口相结合。