公开(公告)号：US09178364B1

公开(公告)日：2015-11-03

申请号：US12209814

申请日：2008-09-12

申请人： Nadim Khlat ,  Alexander Wayne Hietala ,  Chris Ngo

发明人： Nadim Khlat ,  Alexander Wayne Hietala ,  Chris Ngo

IPC分类号： H02J7/00

CPC分类号： H02J7/0065 ,  H02J7/0013

摘要： The present invention relates to estimating a battery current supplied from a battery to a switching power supply, which provides a regulated output signal to a load, based on a switching power supply current in the switching power supply, and then controlling the regulated output signal to limit the battery current to within an acceptable threshold. The switching power supply current may be provided by one or more switching elements in the switching power supply. The switching elements may be mirrored to provide a mirrored switching power supply current, which is used to estimate the battery current. The estimated battery current may include an estimated average battery current, an estimated instantaneous battery current, or both.

摘要翻译： 本发明涉及基于开关电源中的开关电源电流来估计从电池提供给开关电源的电池电流，开关电源向开关电源提供调节的输出信号，然后将调节的输出信号控制到 将电池电流限制在可接受的阈值内。 开关电源电流可以由开关电源中的一个或多个开关元件提供。 开关元件可以被镜像以提供用于估计电池电流的镜像开关电源电流。 估计的电池电流可以包括估计的平均电池电流，估计的瞬时电池电流，或两者。

公开(公告)号：US08068573B1

公开(公告)日：2011-11-29

申请号：US11740967

申请日：2007-04-27

申请人： Nadim Khlat ,  Richard A. Summe ,  Scott Robert Humphreys ,  Chris Ngo

发明人： Nadim Khlat ,  Richard A. Summe ,  Scott Robert Humphreys ,  Chris Ngo

IPC分类号： H04L7/00 ,  H03L7/00

CPC分类号： H03K3/84 ,  H03K7/04 ,  H04B15/06

摘要： The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.

摘要翻译： 本发明是一种相位抖动数字通信系统，其包括数字接收机，并且使用相位抖动来扩展一个或多个系统时钟的能量以最小化接收机去敏感。 相位抖动对每个系统时钟使用单个频率; 然而，每个系统时钟的能量通过改变每个时钟半周期的占空比在一个频率范围内扩展。 非相抖动时钟驱动接收器模拟 - 数字转换器的采样时钟，以提供与接收信息的精确相关性，这可能允许使用比在频率抖动设计中更高频率的采样时钟。 相位抖动时钟和非相位抖动时钟可以具有通过两个整数的比率彼此相关的恒定频率; 因此，用于提取接收到的数据的时基总是相关和准确的。