Bus master interface circuit with transparent preemption of a data
transfer operation
    1.
    发明授权
    Bus master interface circuit with transparent preemption of a data transfer operation 失效
    具有数据传输操作透明度预警的总线主接口电路

    公开(公告)号:US5119480A

    公开(公告)日:1992-06-02

    申请号:US434385

    申请日:1989-11-13

    IPC分类号: G06F13/32 G06F13/362

    CPC分类号: G06F13/32

    摘要: A plurality of specialized controllers (e.g., 202, 204 & 206), each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus (104) and a local bus (106) on a computer adapter card (102). When the Direct Memory Access (DMA) controller (202) is controlling a DMA operation on the local bus, certain other controllers (204 & 206) can break-in to the current DMA operation, temporarily halting the DMA opertion until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit (212) are temporarily blocked by blocking signals from a break-in logic circuit (210). The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.