公开(公告)号：US5119480A

公开(公告)日：1992-06-02

申请号：US434385

申请日：1989-11-13

申请人： Serafin J. E. Garcia, Jr. ,  Douglas R. Chisholm ,  Dean A. Kalman ,  Russell S. Padgett ,  Robert D. Yoder

发明人： Serafin J. E. Garcia, Jr. ,  Douglas R. Chisholm ,  Dean A. Kalman ,  Russell S. Padgett ,  Robert D. Yoder

IPC分类号： G06F13/32 ,  G06F13/362

CPC分类号： G06F13/32

摘要： A plurality of specialized controllers (e.g., 202, 204 & 206), each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus (104) and a local bus (106) on a computer adapter card (102). When the Direct Memory Access (DMA) controller (202) is controlling a DMA operation on the local bus, certain other controllers (204 & 206) can break-in to the current DMA operation, temporarily halting the DMA opertion until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit (212) are temporarily blocked by blocking signals from a break-in logic circuit (210). The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

公开(公告)号：US5524267A

公开(公告)日：1996-06-04

申请号：US220793

申请日：1994-03-31

申请人： Arthur L. Chin ,  Serafin J. E. Garcia, Jr. ,  Don S. Keener ,  Gregory J. Moore ,  Stephanie P. Payne ,  Eric S. Stine

发明人： Arthur L. Chin ,  Serafin J. E. Garcia, Jr. ,  Don S. Keener ,  Gregory J. Moore ,  Stephanie P. Payne ,  Eric S. Stine

IPC分类号： G06F13/22 ,  G06F13/20

CPC分类号： G06F13/22

摘要： A digital bus circuit having an Address/Data port select decoder 170 in circuit communication with a Selector 194, a Data Port Buffer/Register 181, and an Address Port register 208. The Selector 194 is in circuit communication with an auto incrementor 216, an auto decrementor 218, and a polling function. The incrementor 216 serves to automatically increment an address present in the Address port register 208. The decrementor 218 serves to automatically decrement an address present in the Address port register 208. The polling function serves to reload the Address port register 208 with the same address. The present invention allows a number of enhanced programming methods which permit input and output operations to be implemented with fewer program code instructions. One of the programming methods disclosed by the present invention is an enhanced method of "polling" a device's internal register by accessing the polling function.

摘要翻译： 具有与选择器194，数据端口缓冲器/寄存器181和地址端口寄存器208进行电路通信的地址/数据端口选择解码器170的数字总线电路。选择器194与自动增量器216进行电路通信， 自动递减器218和轮询功能。 递增器216用于自动递增地址端口寄存器208中存在的地址。递减器218用于自动递减地址端口寄存器208中存在的地址。轮询功能用于以相同的地址重新加载地址端口寄存器208。 本发明允许使用更少的程序代码指令实现输入和输出操作的许多增强编程方法。 本发明公开的编程方法之一是通过访问轮询功能“轮询”设备的内部寄存器的增强方法。

公开(公告)号：US5513368A

公开(公告)日：1996-04-30

申请号：US93541

申请日：1993-07-16

申请人： Serafin J. E. Garcia, Jr. ,  Gary B. Hoch ,  Eric H. Stelzer ,  Donald G. Williams

发明人： Serafin J. E. Garcia, Jr. ,  Gary B. Hoch ,  Eric H. Stelzer ,  Donald G. Williams

IPC分类号： G06F13/28 ,  G06F9/30 ,  G06F15/16

CPC分类号： G06F13/28

摘要： DMA adapters which perform programmed data transfer operations in response to descriptors are programmed by information in the same descriptors (and adapter logic responsive to that information) to perform various ancillary control functions relative to addressable I/O devices that conventionally would be addressed and controlled directly by a host (higher level) system processor (e.g., the processor that prepares the descriptors). The ancillary control functions are variable programmably in number (e.g., in the disclosed embodiment, one descriptor can define 0, 1 or 2 discrete ancillary control operations) and effects produced by each operation are programmably variable (e.g., ancillary operation can be used by the adapter to alter states of addressed devices; for example, to prepare a device that has been transferring data in one direction, in a half-duplex mode, for transferring data in the opposite direction, or to switch to a full duplex mode, etc.). These functions hitherto have imposed significant processing burdens on the host processor and functional constraints on the adapters and devices; typically, constraints requiring the adapter and one or more devices to be idled for the time required by the host to condition the device(s). Accordingly, delegation of these functions to the adapter, allows them to be carried out without idling of any system elements and while the host is otherwise productively occupied. Also, such delegation creates new applicational possibilities; e.g., having an adapter linked to a communication channel react to remotely originated signals and set up operations tightly coordinated in real time to previously executed operations (for example, retransmission of data previously received with detected error).

摘要翻译： 响应于描述符执行编程数据传输操作的DMA适配器由相同描述符（以及响应于该信息的适配器逻辑）的信息编程，以执行相对于可以直接寻址和控制的可寻址I / O设备的各种辅助控制功能 由主机（较高级别）系统处理器（例如，准备描述符的处理器）。 辅助控制功能可编程地变化（例如，在所公开的实施例中，一个描述符可以定义0,1或2个离散辅助控制操作），并且由每个操作产生的效果是可编程地变化的（例如，辅助操作可以由 适配器来改变寻址设备的状态;例如，准备已经以半双工模式在一个方向上传送数据的设备，用于以相反的方向传送数据，或者切换到全双工模式等。 ）。 这些功能迄今已经对主机处理器施加了显着的处理负担，并在适配器和设备上施加了功能限制; 通常，需要适配器和一个或多个设备在主机调节设备所需的时间内空闲的约束。 因此，将这些功能委派给适配器，允许它们在没有任何系统元件的空闲的情况下被执行，并且主机被有效地占用。 此外，这种授权创造了新的应用可能性; 例如，具有连接到通信信道的适配器对远程发起的信号做出反应并将与实时紧密协调的操作建立到先前执行的操作（例如，先前用检测到的错误接收的数据的重传）。

公开(公告)号：US5448702A

公开(公告)日：1995-09-05

申请号：US24981

申请日：1993-03-02

申请人： Serafin J. E. Garcia, Jr. ,  Michael S. Gatson ,  Gary B. Hoch ,  Eric H. Stelzer ,  Donald G. Williams

发明人： Serafin J. E. Garcia, Jr. ,  Michael S. Gatson ,  Gary B. Hoch ,  Eric H. Stelzer ,  Donald G. Williams

IPC分类号： G06F13/12 ,  G06F13/20 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F13/20

摘要： A processor stores descriptors without explicit linkages, in non-contiguous memory locations, and sequentially hands them off to an adaptor which manages scheduling and processing of data transfers defined by the descriptors. Each descriptor is handed off in a request signalling process in which the processor polls the availability of a request register in the adaptor, and writes the address of a respective descriptor to that register when it is available. The adapter then schedules processing of the descriptor whose address is in the request register. The adapter manages a "Channel Descriptor Table" (CDT), which defines the order of processing of descriptors designated by the requests. In effect, the CDT defines a linked list queue into which the adapter installs descriptors, in the sequence of receipt of respective requests. Using the CDT information, the adapter retrieves successively queued descriptors and controls performance of operations (data transfer or other) defined by them. Accordingly, descriptors in the queue are retrieved and respectively defined operations are performed, in the order of receipt of respective requests; as if the descriptors had been stored by the processor with explicit linking and chaining associations and handed off to the adapter as an explicitly chained set of descriptors. In a preferred embodiment, a "multichannel adapter unit" (MAU), directing data transfers relative to multiple channels, contains one request register for all channels and a separate CDT and "request address port" dedicated to each channel. Requests accompanied by addresses designating these ports are "funneled" through the request register to CDT queues of respective channels. The processor can effectively remove a descriptor from any CDT queue, without potentially compromising handling of data transfers defined by other descriptors in the queue, by writing a "skip code" to the descriptor. Upon retrieving a descriptor with a skip code, the adapter automatically skips the operation defined by that descriptor and chains to a next descriptor (if the queue defined by the CDT is not empty).