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1.
公开(公告)号:US6122435A
公开(公告)日:2000-09-19
申请号:US915728
申请日:1997-08-21
申请人: Masato Izawa , Hiroshi Horikane
发明人: Masato Izawa , Hiroshi Horikane
IPC分类号: H04N5/7826 , G11B5/588 , G11B15/087 , G11B15/467 , G11B20/10 , G11B20/18 , G11B27/032 , G11B27/30 , H04N5/92 , H04N9/804 , H04N9/877 , H04N5/76
CPC分类号: G11B20/1809 , G11B15/087 , G11B15/467 , G11B27/032 , G11B27/3063 , G11B5/588 , H04N9/877 , G11B2220/90 , H04N9/8042
摘要: A digital recording and playback unit which prevents deterioration of reproduced video image due to confusion in servo control occurring at a chronologically discontinued portion in the recording at the time of playback when a wide head is used for reproducing assembled video data recorded in a narrow track width. The digital recording and playback unit include a decoding circuit for decoding the reproducing signal to digital playback data, an error correction circuit for restoring erroneous portions of the data decoded by the decoding circuit, a first frame memory used for making corrections by the error correction circuit, a deshuffling circuit for reassembling data restored by the error correction circuit, a second frame memory used for deshuffling by the deshuffling circuit, a detecting circuit for detecting a chronologically discontinued portion in the recording at the time of playback, and a control circuit for instructing writing and reading to and from the first and second frame memories based on the output of the detecting circuit. Helical scanning is employed and one frame of the video image consisting of multiple tracks is recorded in a track width of 2 W/3, where W is the width of a recording and playback head.
摘要翻译: 一种数字记录和重放单元,其防止由于在使用宽头用于再现以窄轨道宽度记录的组合视频数据时,在播放时在记录中的时间上不连续部分发生的伺服控制中的混乱导致的再现视频图像的劣化 。 数字记录和重放单元包括用于将再现信号解码为数字重放数据的解码电路,用于恢复由解码电路解码的数据的错误部分的纠错电路,用于由纠错电路进行校正的第一帧存储器 ,用于重新组合由纠错电路恢复的数据的去混洗电路,用于由去混洗电路进行混洗的第二帧存储器,用于检测回放时记录中的时间上不连续部分的检测电路,以及用于指示 基于检测电路的输出,对第一和第二帧存储器进行写入和读取。 使用螺旋扫描,并且以2W / 3的轨道宽度记录由多个轨道组成的视频图像的一帧,其中W是记录和回放头的宽度。
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公开(公告)号:US5343501A
公开(公告)日:1994-08-30
申请号:US836660
申请日:1992-02-18
申请人: Shinya Kadono , Masakazu Nishino , Tatsuro Juri , Hiroshi Horikane , Iwao Hidaka
发明人: Shinya Kadono , Masakazu Nishino , Tatsuro Juri , Hiroshi Horikane , Iwao Hidaka
CPC分类号: G06F17/147
摘要: In an apparatus for executing an algorithm for realizing an orthogonal transform operation such as the 8 points fast cosine transform, by operating on successive sets of data values of a digital signal such as a digital video signal in such applications as high efficiency coding of a digital video signal, a plurality of multiplication operations that are executed during processing of each set of data values are executed sequentially by time division multiplex operation of a single multiplier (32) which is capable of executing a multiplication operation within one sample period of the digital signal, with input and output data values being transferred by selector units (11, 33, 41) between the multiplier and other sections of the apparatus at appropriate times during processing of each set of the input digital signal values. The scale of hardware required for the apparatus is thereby reduced by comparison with an apparatus which employs a plurality of separate multipliers.
摘要翻译: 在用于执行诸如8点快速余弦变换的正交变换操作的算法的装置中,通过在诸如数字视频信号的数字信号的数据信号的连续集合上进行操作,例如在数字 视频信号,在每个数据值集合的处理期间执行的多个乘法运算通过在数字信号的一个采样周期内能够执行乘法运算的单个乘法器(32)的时分多路复用操作来顺序执行 ,其中输入和输出数据值由选择器单元(11,33,41)在设备的乘法器和其它部分之间的适当时间在每组输入数字信号值的处理期间传送。 与使用多个单独的乘法器的装置相比,装置所需的硬件规模由此减少。
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公开(公告)号:US5268755A
公开(公告)日:1993-12-07
申请号:US835600
申请日:1992-02-14
申请人: Masakazu Nishino , Tatsuro Juri , Hiroshi Horikane , Iwao Hidaka
发明人: Masakazu Nishino , Tatsuro Juri , Hiroshi Horikane , Iwao Hidaka
CPC分类号: H04N19/18 , H04N19/112 , H04N19/126 , H04N19/136 , H04N19/154 , H04N19/176 , H04N19/124 , H04N19/60
摘要: Disclosed is an orthogonal transformation encoder in which after horizontal orthogonal transformation is performed, in parallel to the horizontal and vertical rearrangement of the coefficients for performing vertical orthogonal transformation, detection of interfield coefficient is performed and intra-frame/intrafield modes for the vertical orthogonal transformation are switched. Further, in parallel to the rearrangement of the transformation coefficients for the vertical orthogonal transformation to be in the ascending order from a lower frequency component to a higher frequency component, the amplitude values of the AC components in the block in question are detected to thereby make control on the basis of the amplitude values so that the smaller the amplitude value of the block the smaller the quantizing step width.
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