Abstract:
A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.
Abstract:
A multi-phase DC-DC converter architecture in which parameters including error signal gains and modulator gains are defined so as to balance multiple converter channel currents, irrespective of whether the converter channels are supplied with the same or different input voltages.
Abstract:
A soft start circuit for a DC-DC converter has an input reference voltage coupled to an error amplifier and to a soft start capacitor. A feedback resistor is coupled between an output node and the error amplifier, whose output is coupled to a pulse width modulator (PWM). The PWM output is coupled through an inductor to the output node, to which an output capacitor referenced to ground is coupled. Means is provided to charge up the soft start capacitor to the output voltage while the converter is disabled. As a result, when enabled, the converter will not discharge the output capacitor, but will ramp the output voltage to the voltage Vref without excessive currents.