Hybrid Cache State And Filter Tracking Of Memory Operations During A Transaction
    1.
    发明申请
    Hybrid Cache State And Filter Tracking Of Memory Operations During A Transaction 有权
    混合缓存状态和过滤器跟踪事务期间的内存操作

    公开(公告)号:US20140006698A1

    公开(公告)日:2014-01-02

    申请号:US13535788

    申请日:2012-06-28

    IPC分类号: G06F12/08 G06F12/00

    摘要: In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,高速缓存存储器可以存储多条高速缓存线,每条高速缓存行包括写入字段以存储写入指示符,以指示在事务性存储器的事务期间是否已经推测写入数据,以及读取集 字段以存储多个读取设置指示符,每个指示符指示对应的线程在交易已经提交之前是否已经读取数据。 与高速缓冲存储器相关联的压缩过滤器包括第一过滤器存储器,用于在事务已经提交之前存储由第一线程线程读取的高速缓存线的高速缓存行地址的表示。 描述和要求保护其他实施例。

    Hybrid cache state and filter tracking of memory operations during a transaction
    2.
    发明授权
    Hybrid cache state and filter tracking of memory operations during a transaction 有权
    混合缓存状态和过滤器跟踪事务期间的内存操作

    公开(公告)号:US09298632B2

    公开(公告)日:2016-03-29

    申请号:US13535788

    申请日:2012-06-28

    摘要: In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,高速缓存存储器可以存储多条高速缓存线,每条高速缓存行包括写入字段以存储写入指示符,以指示在事务性存储器的事务期间是否已经推测写入数据,以及读取集 字段以存储多个读取设置指示符,每个指示符指示对应的线程在交易已经提交之前是否已经读取数据。 与高速缓冲存储器相关联的压缩过滤器包括第一过滤器存储器,用于在事务已经提交之前存储由第一线程线程读取的高速缓存线的高速缓存行地址的表示。 描述和要求保护其他实施例。