公开(公告)号：US20240320030A1

公开(公告)日：2024-09-26

申请号：US18331967

申请日：2023-06-09

Applicant: International Business Machines Corporation

Inventor： Andrew Wright ,  James Anthony Harrison ,  Mark William Trafford Todd ,  William Anthony Fitzgerald ,  Paulo Roberto Pontin Tiziano ,  Mark Andrew Woolley ,  Philip I Wakelin ,  Stephen James Hobson ,  Philip Robert Lee ,  Jenny Jing He

IPC: G06F9/46

CPC classification number: G06F9/467

Abstract: A determination is made whether a requested transaction of a certain type or class is available (i.e., suitable for execution or queueing) within a processing environment. In the case that a transaction of the certain type or class is not available, the request to be rejected is enabled, thus avoiding queuing of the requested transaction. Embodiments may thus provide a mechanism to protect a processing environment by avoiding the overhead of creating and removing specific transactions of the certain type or class.

公开(公告)号：US20240311177A1

公开(公告)日：2024-09-19

申请号：US18511634

申请日：2023-11-16

Applicant: Egnyte, Inc.

Inventor： Upendra Singh ,  Ajay Salpekar ,  Bhaskar Guthikonda ,  Andrew Guerra ,  David Tang

IPC: G06F9/46 ,  G06F8/65 ,  G06F8/71

CPC classification number: G06F9/467 ,  G06F8/65 ,  G06F8/71

Abstract: A system and methods for enhancing content collaboration by conflict detection and resolution. A hybrid cloud cache receives a request from a client to upload an object to the cloud. The hybrid cloud cache may perform an internal lookup to find the latest version of the object known to it. This lookup may return a local identifier or a cloud identifier. The cache may compare a client-provided identifier to the local identifier or to the cloud identifier that is mapped to the local identifier to determine if the client-provided identifier refers to the latest uploaded version of the object. The system may determine that a conflict exists if the client-provided identifier does not match either identifier. The system may generate an alternate name for the object and upload the renamed object to the cloud from the hybrid cloud cache.

公开(公告)号：US20240281278A1

公开(公告)日：2024-08-22

申请号：US18654035

申请日：2024-05-03

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/121 ,  G06F13/16

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: A method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.

公开(公告)号：US12026513B2

公开(公告)日：2024-07-02

申请号：US17108258

申请日：2020-12-01

Applicant: Oracle International Corporation

Inventor： Unmesh Rathi ,  Arjun Sharma ,  Suresh Kumar Neelakanda Iyer ,  Vijayan Satyamoorthy Srinivasa

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/52 ,  G06F11/14

CPC classification number: G06F9/30047 ,  G06F9/467 ,  G06F9/526 ,  G06F11/1446 ,  G06F11/1474 ,  G06F2201/84 ,  G06F2201/87

Abstract: Techniques for providing high-performance buffer caches for transactional input/output (I/O) systems are disclosed. The techniques include obtaining a first logical creation time of a resource to be acquired by the first transaction during a pre-commit phase of a first transaction with an I/O system. When the first logical creation time exceeds a latest logical creation time from a set of resources previously acquired by the first transaction, the first logical creation time of the resource is compared with an earliest logical termination time from the set of resources. When the first logical creation time of the resource exceeds the earliest logical termination time from the set of resources, a conflict between the resource and the set of resources is detected, and a restart of the first transaction is triggered.

公开(公告)号：US12020062B2

公开(公告)日：2024-06-25

申请号：US17074811

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F9/46 ,  G06F12/0815 ,  G06F12/0875

CPC classification number: G06F9/467 ,  G06F12/0815 ,  G06F12/0875

Abstract: Chiplet systems may include a memory controller that has programmable atomic units that execute programmable atomic transactions. These instructions are stored in one or more memory partitions of memory in the programmable atomic unit. Since the programmable atomic unit executes programmable atomic transactions that are customized for various processes, and since the programmable atomic unit is a physical resource shared by multiple processes, the processes need a way of both loading the programmable atomic unit memory with instructions and a method of calling those instructions. Disclosed are methods, systems, and devices for registering, calling, and virtualizing programmable atomic transactions.

公开(公告)号：US20240168795A1

公开(公告)日：2024-05-23

申请号：US18081552

申请日：2022-12-14

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Olivier Giroux ,  Jack H. Choquette ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Rui Guo ,  Chao Li ,  Vishalkumar Ketankumar Mehta ,  David Dastous St. Hilaire ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Subhasmita Chakraborty ,  Vikram Dhar

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54

CPC classification number: G06F9/467 ,  G06F9/3004 ,  G06F9/3877 ,  G06F9/541

Abstract: Apparatuses, systems, and techniques to perform delayed memory transaction information check. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to check for information provided by one or more users about one or more memory transactions after a timeout event indicated by one or more users.

公开(公告)号：US11947994B2

公开(公告)日：2024-04-02

申请号：US16367910

申请日：2019-03-28

Applicant: SAP SE

Inventor： Thomas Legler

IPC: G06F9/46 ,  G06F9/52 ,  G06F12/0817 ,  G06F16/25

CPC classification number: G06F9/467 ,  G06F9/52 ,  G06F12/0828 ,  G06F16/25

Abstract: A method may include determining a threshold quantity of attempts to optimistically perform a first transaction operating data stored in a database. The threshold quantity of attempts may be determined based on an expected workload of the first transaction and/or a workload at the database. The first transaction may be performed optimistically including by tracking cache lines accessed by the first transaction and detecting, based on a second transaction writing to a cache line accessed by the first transaction, a conflict between the first transaction and the second transaction. If the first transaction is not successful performed after the threshold quantity of attempts to optimistically perform the first transaction, the first transaction may be performed in a fallback mode including by acquiring a lock to prevent the second transaction from accessing a same data in the database as the first transaction. Related systems and articles of manufacture are also provided.

公开(公告)号：US20240045692A1

公开(公告)日：2024-02-08

申请号：US17818309

申请日：2022-08-08

Applicant: Xilinx, Inc.

Inventor： Xiao Teng ,  Tejus Siddagangaiah ,  Bryan Lozano ,  Ehsan Ghasemi ,  Rajeev Patwari ,  Elliott Delaye ,  Jorn Tuyls ,  Aaron Ng ,  Sanket Pandit ,  Pramod Peethambaran ,  Satyaprakash Pareek

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC classification number: G06F9/3814 ,  G06F9/467 ,  G06F9/3004

Abstract: Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions based on the replica of the register address space. The transaction instructions and the wait instructions are included in an instruction buffer. The instruction buffer is provided to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the DP array. In another aspect, the instruction buffer is stored in a file for subsequent execution by the microcontroller.

公开(公告)号：US11816032B2

公开(公告)日：2023-11-14

申请号：US17727912

申请日：2022-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson ,  Neelima Muralidharan

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/0808 ,  G06F12/0895 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

公开(公告)号：US11775297B2

公开(公告)日：2023-10-03

申请号：US16651045

申请日：2018-08-21

Applicant: Arm Limited

Inventor： Grigorios Magklis ,  Matthew James Horsnell ,  Stephan Diestelhorst

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/30021 ,  G06F9/30058 ,  G06F9/30076 ,  G06F9/30094 ,  G06F9/3842 ,  G06F9/467

Abstract: In a system providing transactional memory support, a transaction nesting depth testing instruction is provided for triggering processing circuitry 4 to set at least one status value to one of a plurality of states depending on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth is 1 and at least one further state selected when the transaction nesting depth is greater than or less than 1. The supported ISA enables the setting of the at least one status value and a conditional branch conditional on the at least one status value being in the first state to be performed in response to a single transaction nesting depth testing instruction and a single conditional branch instruction.