-
1.发明授权Semiconductor devices including doped metal silicide patterns and related methods of forming such devices 有权包括掺杂金属硅化物图案的半导体器件和形成这种器件的相关方法公开(公告)号：US08367533B2
公开(公告)日：2013-02-05
申请号：US13152406
申请日：2011-06-03
申请人： Jung-Ho Yun , Gil-heyun Choi , Jong-Myeong Lee
发明人： Jung-Ho Yun , Gil-heyun Choi , Jong-Myeong Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823835
摘要： Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.
摘要翻译： 提供半导体器件及其形成方法。 该方法包括在半导体衬底上形成层间电介质，在层间电介质中形成接触孔以露出半导体衬底，在暴露的半导体衬底上形成包括掺杂剂的金属图案，并进行热处理工艺以使半导体衬底 与金属图案形成金属硅化物图案。 热处理工艺包括将掺杂剂扩散到半导体衬底中。
-
2.发明申请Semiconductor Devices Including Doped Metal Silicide Patterns and Related Methods of Forming Such Devices 审中-公开包括掺杂金属硅化物图案的半导体器件和形成这种器件的相关方法公开(公告)号：US20080296696A1
公开(公告)日：2008-12-04
申请号：US12127208
申请日：2008-05-27
申请人： Jung-Ho Yun , Gil-heyun Choi , Jong-Myeong Lee
发明人： Jung-Ho Yun , Gil-heyun Choi , Jong-Myeong Lee
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823835
摘要： Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.
摘要翻译： 提供半导体器件及其形成方法。 该方法包括在半导体衬底上形成层间电介质，在层间电介质中形成接触孔以露出半导体衬底，在暴露的半导体衬底上形成包括掺杂剂的金属图案，并进行热处理工艺以使半导体衬底 与金属图案形成金属硅化物图案。 热处理工艺包括将掺杂剂扩散到半导体衬底中。
-
3.发明申请Semiconductor Devices Including Doped Metal Silicide Patterns and Related Methods of Forming Such Devices 有权包括掺杂金属硅化物图案的半导体器件和形成这种器件的相关方法公开(公告)号：US20110237058A1
公开(公告)日：2011-09-29
申请号：US13152406
申请日：2011-06-03
申请人： Jung-Ho Yun , Gil-heyun Choi , Jong-Myeong Lee
发明人： Jung-Ho Yun , Gil-heyun Choi , Jong-Myeong Lee
IPC分类号： H01L21/225
CPC分类号： H01L21/823814 , H01L21/823835
摘要： Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.
摘要翻译： 提供半导体器件及其形成方法。 该方法包括在半导体衬底上形成层间电介质，在层间电介质中形成接触孔以露出半导体衬底，在暴露的半导体衬底上形成包括掺杂剂的金属图案，并进行热处理工艺以使半导体衬底 与金属图案形成金属硅化物图案。 热处理工艺包括将掺杂剂扩散到半导体衬底中。
-
-
搜索结果
3 条记录 (耗时 0.012 秒)
