公开(公告)号：US08709937B2

公开(公告)日：2014-04-29

申请号：US13533653

申请日：2012-06-26

申请人： In-sun Park ,  Gil-heyun Choi ,  Ji-soon Park ,  Jong-myeong Lee ,  Jong-won Hong ,  Hei-seung Kim

发明人： In-sun Park ,  Gil-heyun Choi ,  Ji-soon Park ,  Jong-myeong Lee ,  Jong-won Hong ,  Hei-seung Kim

IPC分类号： H01L21/4763

CPC分类号： H01L23/48 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76816 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/06 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

摘要翻译： 根据示例性实施例，形成微图案的方法包括在衬底的虚拟区域上形成具有第一宽度的虚拟图案，并且在衬底的有源线区域上形成具有第二宽度的单元图案。 有源线区域可以与虚拟区域相邻，并且第二宽度可以小于第一宽度。 该方法可以进一步包括通过在有源线区域和虚拟区域上形成种子层来形成镶嵌金属化，在基片的整个表面上形成导电材料层，并平坦化导电材料层以形成金属线。

公开(公告)号：US08696921B2

公开(公告)日：2014-04-15

申请号：US12687987

申请日：2010-01-15

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

IPC分类号： H01L21/302

CPC分类号： H01L21/6719 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76877

摘要： In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.

摘要翻译： 在制造半导体器件的方法中，将衬底装载到具有分别执行单元处理的单元处理部的处理室。 单元处理在相应的处理压力下在单元处理部分彼此独立地在衬底上进行。 基板在处理室的各单元处理部分依次进行单元处理。 当从每个单元处理部分传送基板并且没有基板位于单元处理部分时，分别对单元处理部分进行清洁处理。 因此，可以充分防止处理单元的处理缺陷，并且制造装置的操作周期充分延长。

公开(公告)号：US20130134494A1

公开(公告)日：2013-05-30

申请号：US13588393

申请日：2012-08-17

申请人： Jong-Won HONG ,  Hei-Seung KIM ,  Kyoung-hee NAM ,  In-sun PARK ,  Jong-Myeong LEE

发明人： Jong-Won HONG ,  Hei-Seung KIM ,  Kyoung-hee NAM ,  In-sun PARK ,  Jong-Myeong LEE

IPC分类号： H01L29/788 ,  H01L23/532 ,  H01L21/76

CPC分类号： H01L21/76879 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53238 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

摘要翻译： 半导体器件包括填充通过衬底上的绝缘中间层的至少一部分形成并包括铜的沟槽的金属图案，以及金属图案中的包含钽，氮化钽，钛，钛中的至少一种的润湿改善层图案 氮化物，钌，钴和锰。

公开(公告)号：US08422845B2

公开(公告)日：2013-04-16

申请号：US12968488

申请日：2010-12-15

申请人： Pil-Kyu Kang ,  Dae Lok Bae ,  Gil Heyun Choi ,  Jong Myeong Lee

发明人： Pil-Kyu Kang ,  Dae Lok Bae ,  Gil Heyun Choi ,  Jong Myeong Lee

IPC分类号： G02B6/12 ,  G02B6/26 ,  G02B6/28 ,  G02B6/10 ,  G02B6/32

CPC分类号： H01L21/7624 ,  G02B6/02

摘要： A photo-electric integrated circuit device comprises an on-die optical input/output device. The on-die optical input/output device comprises a substrate having a trench, a lower cladding layer disposed in the trench and having an upper surface lower than an upper surface of the substrate, and a core disposed on the lower cladding layer at a distance from sidewalls of the trench and having an upper surface at substantially the same level as the upper surface of the substrate.

摘要翻译： 光电集成电路器件包括一个片上光输入/输出器件。 片上光输入/输出装置包括具有沟槽的衬底，设置在沟槽中的下包层，并且具有比衬底的上表面低的上表面，以及一距离设置在下包层上的芯 从沟槽的侧壁开始并且具有与衬底的上表面基本相同的高度的上表面。

公开(公告)号：US20130005141A1

公开(公告)日：2013-01-03

申请号：US13616910

申请日：2012-09-14

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

IPC分类号： H01L21/768

CPC分类号： H01L21/76846 ,  H01L21/28562 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/10855 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

摘要翻译： 半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。 阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层 阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。 互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

公开(公告)号：US08211793B2

公开(公告)日：2012-07-03

申请号：US12714704

申请日：2010-03-01

申请人： Jong-Myeong Lee ,  Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Won Hong ,  Kyung-In Choi ,  Hyun-Bae Lee

发明人： Jong-Myeong Lee ,  Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Won Hong ,  Kyung-In Choi ,  Hyun-Bae Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole.

摘要翻译： 用于电连接铝和铜互连的结构和形成方法使用电连接铝和铜互连的内部形状来稳定半导体金属化工艺。 为此，铜互连设置在半导体衬底上。 互连感应层和互连插入层依次形成在铜互连上以具有暴露铜互连的接触孔。 接触孔的上直径可以形成为大于其直径。 阻挡层和铝互连填充在接触孔中。 铝互连形成为不通过接触孔直接接触铜互连。

公开(公告)号：US08053374B2

公开(公告)日：2011-11-08

申请号：US12506361

申请日：2009-07-21

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitidation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 对第一阻挡层的暴露部分进行硝化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US20110237058A1

公开(公告)日：2011-09-29

申请号：US13152406

申请日：2011-06-03

申请人： Jung-Ho Yun ,  Gil-heyun Choi ,  Jong-Myeong Lee

发明人： Jung-Ho Yun ,  Gil-heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/225

CPC分类号： H01L21/823814 ,  H01L21/823835

摘要： Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.

摘要翻译： 提供半导体器件及其形成方法。 该方法包括在半导体衬底上形成层间电介质，在层间电介质中形成接触孔以露出半导体衬底，在暴露的半导体衬底上形成包括掺杂剂的金属图案，并进行热处理工艺以使半导体衬底 与金属图案形成金属硅化物图案。 热处理工艺包括将掺杂剂扩散到半导体衬底中。

公开(公告)号：US20110136332A1

公开(公告)日：2011-06-09

申请号：US12960150

申请日：2010-12-03

申请人： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

发明人： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC分类号： H01L21/28 ,  H01L21/31

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

摘要翻译： 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US20100184294A1

公开(公告)日：2010-07-22

申请号：US12687987

申请日：2010-01-15

申请人： Jin-Ho Park ,  Gil-Heyun CHOI ,  Byung-Lyul PARK ,  Jong-Myeong LEE ,  Zung-Sun CHOI ,  Hye-Kyung JUNG

发明人： Jin-Ho Park ,  Gil-Heyun CHOI ,  Byung-Lyul PARK ,  Jong-Myeong LEE ,  Zung-Sun CHOI ,  Hye-Kyung JUNG

IPC分类号： H01L21/311 ,  B08B7/00

CPC分类号： H01L21/6719 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76877

摘要： In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.

摘要翻译： 在制造半导体器件的方法中，将衬底装载到具有分别执行单元处理的单元处理部的处理室。 单元处理在相应的处理压力下在单元处理部分彼此独立地在衬底上进行。 基板在处理室的各单元处理部分依次进行单元处理。 当从每个单元处理部分传送基板并且没有基板位于单元处理部分时，分别对单元处理部分进行清洁处理。 因此，可以充分防止处理单元的处理缺陷，并且制造装置的操作周期充分延长。