-
公开(公告)号：US07916812B2
公开(公告)日：2011-03-29
申请号：US11370521
申请日：2006-03-07
IPC分类号： H04L27/00
CPC分类号： H04L27/2602 , G06F7/72 , H04L27/2655 , H04L27/2656
摘要： Apparatus and methods of determining a modulo count of a synchronization number in a sleep capable system. The synchronization number is stored in a comparison register, and a comparison number equal to the largest power of two multiple of the modulus within a predetermined range is subtracted from the synchronization number. If the difference is zero, the difference is stored in the comparison register, replacing the previous number stored in the register. If the difference is less than zero, the number stored in the register remains unchanged. The comparison number is right shifted, resulting in division by two. The process is repeated for a number of loops equal to the power of two, or until the difference is less than the modulus.
摘要翻译： 在睡眠能力系统中确定同步数的模数的装置和方法。 同步数存储在比较寄存器中，并且从同步数中减去等于预定范围内的模数的两倍的最大功率的比较数。 如果差值为零，则差值存储在比较寄存器中，代替存储在寄存器中的上一个数字。 如果差值小于零，则寄存器中存储的数字保持不变。 比较数字是右移，导致二分。 对于等于2的幂的多个回路重复该过程，或直到该差小于该模数。
-
2.发明授权公开(公告)号：US07693124B2
公开(公告)日：2010-04-06
申请号：US11133089
申请日：2005-05-18
IPC分类号： G06F15/16
CPC分类号： H04L5/0048 , H04L5/0007 , H04L25/0226 , H04L27/2602
摘要： In an OFDM system, multiple (M) interlaces are defined for M non-overlapping sets of frequency subbands, and M slots with fixed indices are also defined. Data streams and pilot are mapped to slots, which are in turn mapped to interlaces based on a slot-to-interlace mapping scheme that can achieve frequency diversity and good performance for all slots. At a transmitter, a slot-to-interlace converter maps the slots to the interlaces. The slot-to-interlace converter includes multiple multiplexers and a control unit. The multiplexers map the M slots to the M interlaces based on the slot-to-interlace mapping scheme. The control unit generates at least one control signal for the multiplexers. The multiplexers may be arranged and controlled in various manners depending on the slot-to-interlace mapping scheme. At a receiver, a complementary interlace-to-slot converter maps the interlaces to the slots.
摘要翻译： 在OFDM系统中，为M个非重叠的频率子带组定义多个（M）交织，并且还定义具有固定索引的M个时隙。 数据流和导频被映射到时隙，这些时隙又被映射到基于可以实现所有时隙的频率分集和良好性能的时隙到交织映射方案的交错。 在发射机处，时隙到隔行转换器将时隙映射到交织。 时隙到隔行转换器包括多个多路复用器和一个控制单元。 多路复用器基于时隙到交错映射方案将M个时隙映射到M个交织。 控制单元为多路复用器生成至少一个控制信号。 可以根据时隙到交错映射方案以多种方式来布置和控制多路复用器。 在接收机处，互补的交错到时隙转换器将交织器映射到时隙。
-
公开(公告)号：US08229014B2
公开(公告)日：2012-07-24
申请号：US11372578
申请日：2006-03-10
CPC分类号： H04L27/265 , G06F17/142
摘要： An FFT processor for an OFDM receiver includes multiple interrelated operational blocks. The FFT processor is configured to perform data demodulation, channel estimation, and fine timing acquisition on received OFDM symbols. The FFT processor incorporates a pipelined FFT engine using a memory architecture shared with channel estimation and demodulation blocks. The combination of the shared memory structure and the pipelined FFT operation enable the channel estimation and demodulation processing to be completed during the time used to capture the next received symbol.
摘要翻译： 用于OFDM接收机的FFT处理器包括多个相互关联的操作块。 FFT处理器被配置为在接收的OFDM符号上执行数据解调，信道估计和精细定时获取。 FFT处理器采用流水线FFT引擎，使用与信道估计和解调块共享的存储架构。 共享存储器结构和流水线FFT操作的组合使得信道估计和解调处理在用于捕获下一个接收到的符号的时间期间完成。
-
-
搜索结果
3 条记录 (耗时 0.013 秒)
