公开(公告)号：US4818716A

公开(公告)日：1989-04-04

申请号：US111690

申请日：1987-10-22

申请人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

发明人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/265 ,  B01J17/00

CPC分类号： H01L27/1126

摘要： Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.

摘要翻译： 公开了具有串联连接的多个MISFET的垂直型只读存储器（ROM）的存储单元。 MISFET包括形成有多个导电层的栅电极，其中一些MISFET被设置为耗尽型，并且至少一些剩余的MISFET被设置为增强型，以便将信息写入存储单元。 信息写入操作通过至少两个步骤进行。 也就是说，在第一信息写入步骤中，使用栅电极作为掩模来注入杂质; 并且在第二步骤中，通过栅电极将杂质注入到半导体衬底的表面中。 这些步骤使得能够生产半导体存储器件，例如具有降低的串联电阻并且适于高度集成的存储单元的垂直型掩模ROM。 此外，公开了一种半导体存储器件的存储结构，其适用于通过多层栅电极的布置而具有更高的集成度。

公开(公告)号：US4904615A

公开(公告)日：1990-02-27

申请号：US301978

申请日：1989-01-26

申请人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

发明人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

IPC分类号： H01L27/112 ,  H01L21/8246

CPC分类号： H01L27/1126

摘要： Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.