公开(公告)号：US4803180A

公开(公告)日：1989-02-07

申请号：US56990

申请日：1987-06-03

Applicant: Mitsuo Ohdate

Inventor： Mitsuo Ohdate

IPC: H01L21/52 ,  H01L21/58 ,  H01L23/049 ,  H01L23/48 ,  H01L25/11 ,  B01J17/00 ,  H01L23/04 ,  H01L23/10

CPC classification number: H01L24/72 ,  H01L23/049 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01033 ,  Y10T29/49169 ,  Y10T29/49918

Abstract: A semiconductor device includes a support member; a semiconductor element mounted on the support member; an elastic body which places the semiconductor element in pressure-contact with the support member; a cylindrical body for containing the semiconductor element and the elastic body, the lower end of the cylindrical body being fixed to the support member; and a plurality of curved projections produced so as to be in contact with the upper end of the elastic body by curving at least three points of the top end of the cylindrical body while pressure is applied to the semiconductor element through the elastic body.

Abstract translation: 一种半导体器件包括：支撑构件; 安装在所述支撑构件上的半导体元件; 将所述半导体元件与所述支撑部件压力接触的弹性体; 用于容纳半导体元件和弹性体的圆柱体，圆柱体的下端固定到支撑构件; 以及多个弯曲突起，其通过弯曲至少三个圆柱体顶端的点而与弹性体的上端接触，同时通过弹性体向半导体元件施加压力。

公开(公告)号：US4769342A

公开(公告)日：1988-09-06

申请号：US917678

申请日：1986-10-10

Applicant: Tetsuya Yagi ,  Hitoshi Kagawa

Inventor： Tetsuya Yagi ,  Hitoshi Kagawa

IPC: H01S5/00 ,  H01L21/304 ,  H01L21/78 ,  H01S5/02 ,  H01S5/026 ,  H01S5/16 ,  H01L21/208 ,  B01J17/00

CPC classification number: H01S5/164 ,  H01L21/3043 ,  H01L21/78 ,  H01S5/0264 ,  H01S5/0201 ,  H01S5/0202 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/065 ,  Y10S148/095

Abstract: A semiconductor laser device comprises a substrate (7) formed of p type GaAs, a laser diode portion (10) capable of laser oscillation and a monitor photodiode portion (11) capable of photoelectric conversion formed on substrate (7). The laser diode portion (10) and the monitor photodiode portion (11) are both formed of an epitaxial separating layer (6) of p type AlAs, an epitaxial layer group (23) mainly formed of a material of AlGaAs system and an epitaxial window layer (9) formed on a cleavage plane of this epitaxial layer group (23). The cleavage plane of the epitaxial window layer (9) on the side of the laser diode portion (10) constitutes a laser resonator plane (16) for laser light output of said laser diode portion (10) while the cleavage plane of the epitaxial window layer (9) on the monitor photodiode portion (11) constitutes a light receiving plane (17) for receiving the laser light outputted from the laser resonator plane (16).

Abstract translation: 半导体激光器件包括由p型GaAs形成的衬底（7），能够激光振荡的激光二极管部分（10）和能够在衬底（7）上形成光电转换的监视器光电二极管部分（11）。 激光二极管部分（10）和监视光电二极管部分（11）均由p型AlAs的外延分离层（6），主要由AlGaAs体系的材料形成的外延层组（23）和外延窗 层（9）形成在该外延层组（23）的解理面上。 激光二极管部分（10）侧的外延窗口层（9）的解理面构成激光二极管部分（10）的激光输出的激光谐振器平面（16），同时外延窗口的解理面 监视器光电二极管部分（11）上的层（9）构成用于接收从激光谐振器平面（16）输出的激光的光接收平面（17）。

公开(公告)号：US4618396A

公开(公告)日：1986-10-21

申请号：US675400

申请日：1984-11-27

Applicant: Takashi Shimoda ,  Masami Sasaki

Inventor： Takashi Shimoda ,  Masami Sasaki

IPC: C30B15/04 ,  C30B15/00 ,  C30B27/02 ,  C30B29/42 ,  B01J17/00 ,  C01B27/00 ,  C04B35/00

CPC classification number: C30B15/00 ,  C30B29/42

Abstract: A GaAs single crystal is disclosed containing at least one impurity selected from the group consisting of In, Al, C and S, in which fluctuation of the concentration of the impurity is less that 20% throughout the crystal from which wafers having uniform characteristics can be produced, and which may be prepared by a process comprising, at a high temperature and under high pressure, pulling up the single crystal from a raw material melt containing simple substances Ga and As or GaAs compound as well as at least one impurity while controlling the concentration of As so as to keep a distribution coefficient of the impurity in GaAs within 1.+-.0.1.

Abstract translation: 公开了一种GaAs单晶，其包含选自In，Al，C和S中的至少一种杂质，其中杂质浓度的波动在整个晶体中的均匀特性的晶体可以具有小于20％ 并且其可以通过包括在高温和高压下从包含简单物质Ga和As或GaAs化合物的原料熔体以及至少一种杂质中提取单晶的方法来制备，同时控制 As的浓度使GaAs中的杂质分布系数保持在1 +/- 0.1内。

公开(公告)号：US4474639A

公开(公告)日：1984-10-02

申请号：US524440

申请日：1983-08-18

Applicant: Otmar Fritz

Inventor： Otmar Fritz

IPC: H01L21/60 ,  H01L21/68 ,  B01J17/00

CPC classification number: H01L24/86 ,  H01L21/6835 ,  H01L2221/68313 ,  H01L2221/68354 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T156/1092 ,  Y10T156/1744 ,  Y10T156/1759 ,  Y10T29/53178

Abstract: For the purpose of processing individual, integrated circuits into film-mounted, integrated circuits (micropacks), a plate having recesses exhibiting the size of the individual chips disposed matrix-like is secured to a highly plane-parallel carrier plate consisting of material exhibiting poor thermal conductivity, the individual chips are placed in the recess of said plate, and the overall arrangement is further processed in an automatic contacting machine in a known manner.

Abstract translation: 为了将单独的集成电路加工成胶片安装的集成电路（微孔），具有表现出矩阵状的各个芯片的尺寸的凹部的板被固定到由平面平行的载体板组成的材料上 导热性，将各个芯片放置在所述板的凹部中，并且以已知的方式在自动接触机器中进一步处理整体布置。

公开(公告)号：US4468799A

公开(公告)日：1984-08-28

申请号：US372886

申请日：1982-04-29

Applicant: Margret Harms ,  Holger Luthje ,  Bernd Matthiessen

Inventor： Margret Harms ,  Holger Luthje ,  Bernd Matthiessen

IPC: G03F1/22 ,  H01L21/027 ,  B01J17/00

CPC classification number: G03F1/22

Abstract: The manufacture of semiconductor systems by means of radiation lithography requires low-stress masks when it is important to achieve very fine structures. In accordance with the invention, such a mask comprises a carrier of boron-doped silicon, a radiation absorbing pattern consisting of a double layer of different metals, such as molybdenum and tungsten, or a double layer of layers of the same metal, such as molybdenum, which are deposited in a different manner.

Abstract translation: 通过放射光刻技术制造半导体系统，当重要的是实现非常精细的结构时，需要低应力掩模。 根据本发明，这种掩模包括硼掺杂硅的载体，由不同金属（例如钼和钨）的双层或同一金属层的双层组成的辐射吸收图案，例如 钼，它们以不同的方式沉积。

公开(公告)号：US4441246A

公开(公告)日：1984-04-10

申请号：US147433

申请日：1980-05-07

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L21/321 ,  H01L21/8242 ,  H01L27/108 ,  B01J17/00 ,  H01L21/306 ,  H01L27/04

CPC classification number: H01L27/1085 ,  H01L21/32105 ,  H01L27/10805

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by an improved process employing selective oxidation of polysilicon using PN junction capacitors. A relatively flat surface results from the process, which is favorable to patterning small geometries. The PN junction storage capacitors have improved alpha particle protection. Metal-to-polysilicon gate contacts are made at silicide areas over polysilicon gates; the silicide lowers resistance of the poly elements.

Abstract translation: 一个晶体管N沟道硅栅极型的动态读/写存储单元是通过使用PN结电容器选择性氧化多晶硅的改进工艺制成的。 相对平坦的表面由该方法产生，这有利于图案化的几何形状。 PN结储存电容器具有改进的α粒子保护。 金属到多晶硅栅极触点在多晶硅栅极的硅化物区域上制成; 硅化物降低了多元素的电阻。

公开(公告)号：US4419142A

公开(公告)日：1983-12-06

申请号：US313324

申请日：1981-10-20

Applicant: Naohiro Matsukawa

Inventor： Naohiro Matsukawa

IPC: H01L21/321 ,  H01L21/762 ,  H01L21/312 ,  B01J17/00 ,  C03C15/00

CPC classification number: H01L21/76213 ,  H01L21/321 ,  H01L21/76216 ,  Y10S148/07 ,  Y10S148/106 ,  Y10S148/114 ,  Y10S148/122

Abstract: A method of manufacturing a semiconductor device which comprises the steps of: forming on a semiconductor substrate a layer of a material more quickly oxidizable than the semiconductor substrate; selectively oxidizing only that portion of the layer which is mounted on the element region of the semiconductor substrate; removing at least part of said oxidized layer; and wet oxidizing the retained portion of said more oxidizable material layer to provide an element-isolating oxide layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成比半导体衬底更快速氧化的材料层; 仅选择性地氧化安装在半导体衬底的元件区域上的层的那部分; 去除所述氧化层的至少一部分; 并湿润氧化所述更可氧化的材料层的保留部分以提供元件隔离氧化物层。

公开(公告)号：US4406710A

公开(公告)日：1983-09-27

申请号：US311684

申请日：1981-10-15

Applicant: Roderick D. Davies ,  David B. Scott

Inventor： Roderick D. Davies ,  David B. Scott

IPC: H01L21/033 ,  H01L21/8238 ,  H01L21/265 ,  B01J17/00

CPC classification number: H01L21/8238 ,  H01L21/033

Abstract: CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region.Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative doping effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.

Abstract translation: 仅使用单个掩蔽步骤形成两种导电类型的CMOS源极/漏极区域。 一种掺杂剂被施加到两种类型的源极/漏极区域，并且第二掺杂剂以更高的剂量和能量被施加到仅一种类型的源极/漏极区域。 优选地，硼和砷用作硅中的掺杂剂，因为协同掺杂效应导致反掺杂的源/漏区中的硼完全包含在砷扩散内。

公开(公告)号：US4391032A

公开(公告)日：1983-07-05

申请号：US282706

申请日：1981-07-13

Applicant: Heinz Schulte

Inventor： Heinz Schulte

IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L29/92 ,  H01L21/20 ,  B01J17/00

CPC classification number: H01L28/40 ,  H01L27/10805 ,  H01L27/1085

Abstract: Method for manufacturing dynamic RAM one-transistor storage cells in a semiconductor chip with each cell having one integrated field effect transistor and one integrated capacitor. A semiconductor substrate surface is covered in part by a thin oxide layer and in part by a thick oxide structure. The thin oxide layer is subjected to a first ion implantation. A doped polycrystalline semiconductor material is deposited over the entire surface. The polycrystalline layer is structured by means of a photoresist mask and the underlying layers at the open places etched away to expose substrate surface. The mask is removed. A second thin oxide layer is created by oxidation over the entire surface. A second ion implantation implants ions in the second oxide layer. A second doped layer of polycrystalline material is deposited over the second layer. The second polycrystalline layer is structured by a suitable phototechnique to produce a polycrystalline structure semiconductor layer.

Abstract translation: 用于制造半导体芯片中的动态RAM单晶体管存储单元的方法，每个单元具有一个集成场效应晶体管和一个集成电容器。 半导体衬底表面部分由薄的氧化物层部分地覆盖，并且部分由厚的氧化物结构覆盖。 对薄氧化层进行第一离子注入。 掺杂的多晶半导体材料沉积在整个表面上。 多晶层通过光致抗蚀剂掩模构成，并且在开放位置处的下层被腐蚀掉以暴露衬底表面。 去除面具。 通过在整个表面上的氧化产生第二薄氧化物层。 第二离子注入在第二氧化物层中注入离子。 多晶材料的第二掺杂层沉积在第二层上。 第二多晶层由合适的光电技术构成以产生多晶结构半导体层。

公开(公告)号：US4385947A

公开(公告)日：1983-05-31

申请号：US287936

申请日：1981-07-29

Applicant: Mark A. Halfacre ,  David S. Pan

Inventor： Mark A. Halfacre ,  David S. Pan

IPC: H01L21/033 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/225 ,  B01J17/00

CPC classification number: H01L21/033 ,  H01L21/76218 ,  H01L21/823878 ,  H01L29/0638

Abstract: CMOS transistors are fabricated in a P substrate by applying a first mask with an opening for introducing N type impurities to form a well, applying a second mask layer of oxidation inhibiting material over the region in which the transistors are to be formed; applying a third mask layer over the well, introducing P type impurities into the surface of the substrate using the second and third masking layers to form a guard ring except in the N- well regions and the regions in which the N channel MOS transistors are to be formed, oxidizing the substrate using said second mask to form a thick oxide layer on said substrate except on the transistor regions with the guard ring vertically displaced from the regions in which the transistors are to be formed, introducing P impurities in the channel region of the CMOS transistors and forming CMOS transistors in said transistor regions.A CMOS process capable of the fabrication of N and P channel devices with channel lengths down to the submicron region by the proper adjustment of doping levels and implant doses in the N type well and the P and N channel regions, with no major changes in the basic process flow.

Abstract translation: 通过施加具有用于引入N型杂质的开口的第一掩模以形成阱，在P基板中制造CMOS晶体管，在要形成晶体管的区域上施加氧化抑制材料的第二掩模层; 在阱上施加第三掩模层，使用第二和第三掩模层将P型杂质引入衬底的表面，以形成保护环，除了N阱区和N沟道MOS晶体管所在的区域 使用所述第二掩模氧化所述衬底，以在所述衬底上形成厚氧化物层，除了所述晶体管区域上，所述保护环与要形成所述晶体管的区域垂直偏离，在所述衬底的沟道区域中引入P杂质 CMOS晶体管并在所述晶体管区域中形成CMOS晶体管。 一种能够通过适当调整N型阱和P型和N沟道区中的掺杂水平和注入剂量来制造通道长度低于亚微米区域的N沟道器件和P沟道器件的CMOS工艺， 基本流程。