公开(公告)号：US4988893A

公开(公告)日：1991-01-29

申请号：US075806

申请日：1987-07-20

申请人： Martine Bonneau ,  Gerard Boudon ,  Jean-Claude Le Garrec ,  Pierre Mollier ,  Frank Wallart

发明人： Martine Bonneau ,  Gerard Boudon ,  Jean-Claude Le Garrec ,  Pierre Mollier ,  Frank Wallart

IPC分类号： H03K3/3562 ,  H03K3/356

CPC分类号： H03K3/356017 ,  H03K3/356113

摘要： The invention provides novel implementations of a latch cell in CMOS gate array technology to produce latch dissymmetry and permit a single ended data input. The dissymmetry is produced by increasing the output impedance of the second stage of the latch cell, which can be done, either in a DC or in an AC mode, or even in a mixed version of both modes.

公开(公告)号：US5038192A

公开(公告)日：1991-08-06

申请号：US504153

申请日：1990-04-03

申请人： Martine Bonneau ,  Eric Gouze ,  Robert Hornung ,  Ieng Ong ,  Jean-Marc Piccino

发明人： Martine Bonneau ,  Eric Gouze ,  Robert Hornung ,  Ieng Ong ,  Jean-Marc Piccino

IPC分类号： H01L21/82 ,  H01L27/118

CPC分类号： H01L27/11807

摘要： A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, . . . ) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g., CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one larger PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, . . . ) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.