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公开(公告)号：US20140306740A1
公开(公告)日：2014-10-16
申请号：US13479471
申请日：2012-05-24
申请人： Matthew C. Guyton
发明人： Matthew C. Guyton
CPC分类号： H03K23/58 , H03K23/667
摘要： Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
摘要翻译： 描述了基于从接收信号产生的时间交织信号的多模式分频器和事件计数器。 对于分频器，从接收的时钟信号产生的每个时间交织的时钟信号被提供给位计数器，并且来自每个位计数器的输出信号被提供给多路复用器。 多路复用器选择模块控制来自位计数器的输出信号中的哪一个在时间上在多路复用器的输出处呈现。 时间交织的时钟信号中的位的转换频率允许诸如位计数器之类的各种电路部件被实现为CMOS部件。 因此，分频器比在高时钟频率下工作的常规分频器电路更省电。
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公开(公告)号：US08847637B1
公开(公告)日：2014-09-30
申请号：US13479471
申请日：2012-05-24
申请人： Matthew C. Guyton
发明人： Matthew C. Guyton
CPC分类号： H03K23/58 , H03K23/667
摘要： Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
摘要翻译： 描述了基于从接收信号产生的时间交织信号的多模式分频器和事件计数器。 对于分频器，从接收的时钟信号产生的每个时间交织的时钟信号被提供给位计数器，并且来自每个位计数器的输出信号被提供给多路复用器。 多路复用器选择模块控制来自位计数器的输出信号中的哪一个在时间上在多路复用器的输出处呈现。 时间交织的时钟信号中的位的转换频率允许诸如位计数器之类的各种电路部件被实现为CMOS部件。 因此，分频器比在高时钟频率下工作的常规分频器电路更省电。
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公开(公告)号：US20080186077A1
公开(公告)日：2008-08-07
申请号：US11671525
申请日：2007-02-06
申请人： Matthew C. Guyton , Hae-Seung Lee
发明人： Matthew C. Guyton , Hae-Seung Lee
IPC分类号： G06G7/18
CPC分类号： G06G7/186
摘要： Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The switched-capacitor network includes multiple switches, each having a respective threshold voltage and connected to one of a high-limit voltage, a low-limit voltage, and electrical ground. A first comparator input terminal in communication with the switched-capacitor network is configured to receive a node voltage therefrom during a first phase. The second input terminal is configured to receive one of the high-limit voltage and the low-limit voltage. The voltage-offset network provides a voltage shift at the first input terminal setting an input reference level at a mid-level voltage with respect to the high-limit voltage and the low-limit voltage. The voltage shift enables the first terminal to receive full-swing voltages when the high-limit voltage is less than twice the threshold voltage, with power supply voltages below twice the threshold voltage.
摘要翻译： 描述了用于执行模拟电路功能的开关电容器网络和方法。 电路包括开关电容网络，比较器和电压 - 偏移网络。 开关电容器网络包括多个开关，每个开关具有相应的阈值电压并且连接到高限电压，低限电压和电接地中的一个。 与开关电容器网络通信的第一比较器输入端被配置为在第一阶段期间从其接收节点电压。 第二输入端子被配置为接收高限电压和低限电压中的一个。 电压偏移网络在第一输入端提供电压偏移，将相对于高限电压和低限电压的中间电压设置为输入参考电平。 当高电压电压低于阈值电压的两倍时，电压电压低于阈值电压的两倍，电压漂移使得第一端子能够接收全摆幅电压。
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公开(公告)号：US10348345B2
公开(公告)日：2019-07-09
申请号：US15410427
申请日：2017-01-19
申请人： Matthew C. Guyton , Xiao Wang
发明人： Matthew C. Guyton , Xiao Wang
IPC分类号： H03H7/30 , H04B1/10 , H04L1/00 , H04B1/16 , H04B7/005 , H04L25/02 , H04L25/03 , H04L27/01 , H04L27/22 , H04L27/38
摘要： Methods and systems for equalization of a first receiver. A method may include receiving an input signal at the first receiver. The method may also include receiving the input signal at a second receiver. The method may further include determining, from an output response of the second receiver, an estimate of an out-of-channel interferer present in the input signal. The method may also include determining an estimate, of an undesired in-channel response of the first receiver to the out-of-channel interferer present in the input signal. The method may include applying the estimate, of the undesired in-channel response of the first receiver to the out-of-channel interferer present in the input signal, to an output signal of the first receiver to substantially cancel an instance of an undesired in-channel response of the first receiver to the out-of-channel interferer.
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公开(公告)号：US07564273B2
公开(公告)日：2009-07-21
申请号：US11671525
申请日：2007-02-06
申请人： Matthew C. Guyton , Hae-Seung Lee
发明人： Matthew C. Guyton , Hae-Seung Lee
IPC分类号： G11C27/02
CPC分类号： G06G7/186
摘要： Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The switched-capacitor network includes multiple switches, each having a respective threshold voltage and connected to one of a high-limit voltage, a low-limit voltage, and electrical ground. A first comparator input terminal in communication with the switched-capacitor network is configured to receive a node voltage therefrom during a first phase. The second input terminal is configured to receive one of the high-limit voltage and the low-limit voltage. The voltage-offset network provides a voltage shift at the first input terminal setting an input reference level at a mid-level voltage with respect to the high-limit voltage and the low-limit voltage. The voltage shift enables the first terminal to receive full-swing voltages when the high-limit voltage is less than twice the threshold voltage, with power supply voltages below twice the threshold voltage.
摘要翻译： 描述了用于执行模拟电路功能的开关电容器网络和方法。 电路包括开关电容网络，比较器和电压 - 偏移网络。 开关电容器网络包括多个开关，每个开关具有相应的阈值电压并且连接到高限电压，低限电压和电接地中的一个。 与开关电容器网络通信的第一比较器输入端被配置为在第一阶段期间从其接收节点电压。 第二输入端子被配置为接收高限电压和低限电压中的一个。 电压偏移网络在第一输入端提供电压偏移，将相对于高限电压和低限电压的中间电压设置为输入参考电平。 当高电压电压低于阈值电压的两倍时，电压电压低于阈值电压的两倍，电压漂移使得第一端子能够接收全摆幅电压。
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公开(公告)号：US20180048340A1
公开(公告)日：2018-02-15
申请号：US15410427
申请日：2017-01-19
申请人： Matthew C. Guyton , Xiao Wang
发明人： Matthew C. Guyton , Xiao Wang
CPC分类号： H04B1/1036 , H04B1/0028 , H04B1/1027 , H04B1/1638 , H04B7/005 , H04L1/00 , H04L25/022 , H04L25/0222 , H04L25/03019 , H04L27/01 , H04L27/22 , H04L27/38
摘要： Methods and systems for equalization of a first receiver. A method may include receiving an input signal at the first receiver. The method may also include receiving the input signal at a second receiver. The method may further include determining, from an output response of the second receiver, an estimate of an out-of-channel interferer present in the input signal. The method may also include determining an estimate, of an undesired in-channel response of the first receiver to the out-of-channel interferer present in the input signal. The method may include applying the estimate, of the undesired in-channel response of the first receiver to the out-of-channel interferer present in the input signal, to an output signal of the first receiver to substantially cancel an instance of an undesired in-channel response of the first receiver to the out-of-channel interferer.
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