公开(公告)号：US11838023B2

公开(公告)日：2023-12-05

申请号：US17526225

申请日：2021-11-15

申请人： INTEVA PRODUCTS FRANCE SAS

发明人： François Breynaert ,  Simon Herpin ,  Mohamed Benderradji

IPC分类号： H03K23/58

CPC分类号： H03K23/58

摘要： A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage delivered by the voltage supply. The rotation of the rotor generates a mechanical force that drives a component. A ripple count circuit is configured to filter the drive current based on a rotational speed (ω) of the rotor, and to generate a pulsed output signal indicative of the rotational speed (ω) of the rotor and a rotational position (θ) of the rotor.

公开(公告)号：US20230358608A1

公开(公告)日：2023-11-09

申请号：US18332215

申请日：2023-06-09

申请人： Sony Semiconductor Solutions Corporation

发明人： Hongbo Zhu ,  Kazuki Hizu ,  Takafumi Takatsuka ,  Yusuke Oike ,  Jun Ogi ,  Yoshiaki Tashiro

IPC分类号： G01J1/44 ,  G01J11/00 ,  H03K23/58 ,  H01L31/02

CPC分类号： G01J1/44 ,  G01J11/00 ,  H03K23/58 ,  H01L31/02027 ,  G01J2001/448 ,  G02B5/20

摘要： A light-receiving apparatus (1a) includes a counting unit (11), a setting unit (12), and an acquiring unit (13). The counting unit is configured to measure a detection number of times that represents the number of times incidence of a photon to a light-receiving element has been detected within an exposure period and to output a counted value. The setting unit is configured to set a cycle of updating time information in accordance with an elapsed time during the exposure period. The acquiring unit is configured to acquire the time information indicating a time at which the counted value reaches a threshold before the exposure period elapses.

公开(公告)号：US09806721B2

公开(公告)日：2017-10-31

申请号：US14602377

申请日：2015-01-22

申请人： Samsung Electronics Co., Ltd.

发明人： Kyung-min Kim ,  Kyoung-min Koh ,  Yoon-seok Han

IPC分类号： H03M1/34 ,  H03K23/50 ,  H03K23/58 ,  H04N5/378 ,  H03K21/10

CPC分类号： H03K23/50 ,  H03K21/10 ,  H03K23/58 ,  H04N5/378

摘要： A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhanced operation speed and reduced power consumption.

公开(公告)号：US09024655B2

公开(公告)日：2015-05-05

申请号：US13772759

申请日：2013-02-21

申请人： Wave Semiconductor, Inc.

发明人： Gajendra Prasad Singh

IPC分类号： H03K19/00 ,  H03K19/094

CPC分类号： H03K19/0013 ,  H03K19/094 ,  H03K19/09425 ,  H03K19/096 ,  H03K19/23 ,  H03K23/40 ,  H03K23/58

摘要： Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

摘要翻译： 多阈值闪存Null Convention Logic（NCL）在闪存NCL门内包括一个或多个高阈值电压晶体管，以减少由NCL门晶体管的电流泄漏引起的功耗。 可以添加高阈值电压晶体管和/或可以代替NCL门的一个或多个低电压阈值晶体管。 上拉路径中包含高Vt器件，以在闪存NCL逻辑门处于空状态时降低功耗。

公开(公告)号：US07289591B2

公开(公告)日：2007-10-30

申请号：US11160832

申请日：2005-07-12

申请人： Kang Youl Lee

发明人： Kang Youl Lee

IPC分类号： H03K21/00

CPC分类号： H03K23/62 ,  H03K23/58

摘要： Disclosed herein is a counter circuit for controlling an off-chip driver, wherein hexadecimal number counting is performed using a N (N is a natural number) number of T-flip-flops. The plurality of the T-flip-flops performs a hexadecimal number counting operation to generate 4-bit, 5-bit and 6-bit off-chip driver control signals having a logic value of 16, 32 or 64. A plurality of counting controllers controls the counting operation of the T-flip-flops to increase or decrease the logic value of the control signals for controlling the off-chip driver.

摘要翻译： 这里公开了一种用于控制片外驱动器的计数器电路，其中使用N（N是自然数）T型触发器执行十六进制数计数。 多个T形触发器执行十六进制数计数操作，以产生逻辑值为16,32或64的4位，5位和6位片外驱动器控制信号。多个计数控制器 控制T型触发器的计数操作以增加或减少用于控制片外驱动器的控制信号的逻辑值。

公开(公告)号：US20050017777A1

公开(公告)日：2005-01-27

申请号：US10735336

申请日：2003-12-12

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： H03L7/00 ,  H03K23/58 ,  H03L7/081 ,  H03L7/089 ,  H03K21/00

CPC分类号： H03L7/0805 ,  H03K23/58 ,  H03L7/0814 ,  H03L7/089

摘要： A divider of a DLL(delay locked loop) measures tAC for various periods due to variation of process, temperature and a supply voltage and provides a divided clock having an optimum tAC. The clock divider includes a clock dividing unit, a test mode clock providing unit and a normal mode clock providing unit. The clock dividing unit receives a source clock of the DLL to generate a plurality of divided clocks, each having a period different from each other. The test mode clock providing unit selectively outputs the plurality of the divided clocks in a test mode in response to a test mode signal and a test mode period selecting signal. And, the normal mode clock providing unit outputs selected one of the plurality of the divided clocks in a normal mode in response to the test mode signal.

摘要翻译： DLL（延迟锁定环）的分频器由于过程，温度和电源电压的变化而测量各种周期的tAC，并且提供具有最佳tAC的分频时钟。 时钟分频器包括时钟分频单元，测试模式时钟提供单元和正常模式时钟提供单元。 时钟分割单元接收DLL的源时钟以产生多个具有彼此不同的周期的分割时钟。 测试模式时钟提供单元响应于测试模式信号和测试模式周期选择信号，以测试模式选择性地输出多个划分的时钟。 并且，正常模式时钟提供单元响应于测试模式信号以正常模式输出所选择的多个分频时钟之一。

公开(公告)号：US20020036935A1

公开(公告)日：2002-03-28

申请号：US09950817

申请日：2001-09-13

申请人： Pohang University of Science and Technology Foundation

发明人： Hong-June Park ,  Sang-Hoon Lee

IPC分类号： G11C029/00

CPC分类号： H03K23/58

摘要： A programmable high speed frequency divider, in which the construction of flip-flops for forming a frequency divider which is capable of programming the dividing ratio of an input clock frequency is simplified in order to increase the operation speed of the frequency divider, is provided. By simplifying the structures of least significant bit flip-flops, including the flip-flop representing the least significant bit, among flip-flops forming a frequency divider, the operation speed of the counter in the frequency divider is increased and the frequency limit of an input clock which can be divided is raised.

摘要翻译： 提供了一种可编程高速分频器，其中为了提高分频器的操作速度，提供了用于形成能够编程输入时钟频率的分频比的分频器的触发器的构造。 通过在形成分频器的触发器中简化包括表示最低有效位的触发器的最低有效位触发器的结构，分频器中的计数器的操作速度增加，并且频率限制 可分为输入时钟。

公开(公告)号：US4741004A

公开(公告)日：1988-04-26

申请号：US913048

申请日：1986-09-29

申请人： Michael G. Kane

发明人： Michael G. Kane

IPC分类号： H03K23/58 ,  H03K23/66

CPC分类号： H03K23/58 ,  H03K23/665

摘要： A programmable divide-by-N counter employs a plurality of speed enhancement techniques to provide an overall operational speed corresponding to the speed at which a single-clocked flip-flop is capable of being toggled. The counter configuration provides flexibility in selecting the value of N, the programmable divisor, as well as the possibility of increasing the length the counting chain without producing a reduction in overall operational speed. The speed enhancement techniques are primarily located in the reset logic portion of the counter. A key aspect utilized through-out the overall circuit is that critical signal propagation paths in terms of speed of operation present no more than four gate delay intervals in total response time.

摘要翻译： 可编程分频N计数器采用多种速度增强技术来提供对应于单时钟触发器能够被切换的速度的总体操作速度。 计数器配置提供了选择N值（可编程除数）的灵活性，以及​​增加计数链的长度的可能性，而不会降低总体操作速度。 速度增强技术主要位于计数器的复位逻辑部分。 通过整体电路利用的一个关键方面是，关于运行速度的关键信号传播路径在总响应时间内不超过四个门延迟间隔。

公开(公告)号：US4493095A

公开(公告)日：1985-01-08

申请号：US378356

申请日：1982-05-14

申请人： Akira Yazawa

发明人： Akira Yazawa

IPC分类号： H03K21/38 ,  H03K23/00 ,  H03K23/58 ,  H03K23/66 ,  H03K21/32 ,  H03K21/34

CPC分类号： H03K21/38 ,  H03K23/58

摘要： An improved counter wherein consecutively cascaded flip-flops of the prior art are divided into two groups. A first detector produces a first signal in response to a predetermined set of flip-flop states of the first group. A second detector produces a second signal in response to a predetermined set of flip-flop states of the second group. A third detector produces a count output in response to simultaneous existence of the first and second signals. The output from the first group is arranged in phase so that the second signal may be produced before the count output is produced, by applying an inverted output of the first group to the input of the second group.

摘要翻译： 一种改进的计数器，其中先有技术的连续级联的触发器被分成两组。 第一检测器响应于第一组的预定触发器状态集合产生第一信号。 第二检测器响应于第二组的预定触发器状态集合产生第二信号。 第三检测器响应于同时存在第一和第二信号而产生计数输出。 来自第一组的输出被同相布置，使得可以在产生计数输出之前产生第二信号，通过将第一组的反相输出应用于第二组的输入。

公开(公告)号：US4399549A

公开(公告)日：1983-08-16

申请号：US293918

申请日：1981-08-18

申请人： Gopal K. Srivastava

发明人： Gopal K. Srivastava

IPC分类号： H03K21/08 ,  H03K21/36 ,  H03K23/24

CPC分类号： H03K23/58 ,  H03K21/08

摘要： A method and apparatus is described for dividing a clock frequency by any odd number to obtain a symmetrical output. Generally, some dividers in a chain of divide-by-two dividers are designated as controlled dividers and others are designated as uncontrolled dividers. The clock input of each controlled divider receives the output of an exclusive NOR gate, the inputs to which include the output of the last divider in the chain and either the clock signal or the output of a preceding divider, depending on certain criteria. The clock input of each uncontrolled divider receives the output of an immediately preceding divider. With this arrangement, the last divider in the chain develops a divided output which is symmetrical.

摘要翻译： 描述了用于将时钟频率除以任何奇数以获得对称输出的方法和装置。 一般来说，分隔线分隔线的一些分隔线被指定为受控分隔线，而其他分隔线被指定为不受控制的分隔线。 根据某些标准，每个受控分频器的时钟输入接收异或门的输出，其输入包括链中最后一个分频器的输出，以及时钟信号或前一分频器的输出。 每个不受控制的分频器的时钟输入接收前一分频器的输出。 利用这种布置，链中的最后一个分隔器产生对称的分割输出。