公开(公告)号：US06194940B1

公开(公告)日：2001-02-27

申请号：US09406533

申请日：1999-09-27

申请人： Michael James Hunter ,  Donald H. Friedberg

发明人： Michael James Hunter ,  Donald H. Friedberg

IPC分类号： G06F104

CPC分类号： G06F9/30083

摘要： A clock switch controller has a clock status register which stores current clock data which identifies which of two or more clock signal sources is a current clock signal source currently in use as a system clock signal source. State machine logic of the controller automatically switches, in response to a clock switch signal, the system clock signal source from the current clock signal source to a new clock signal source of the two or more clock signal sources.

摘要翻译： 时钟切换控制器具有时钟状态寄存器，该时钟状态寄存器存储当前时钟数据，该时钟数据识别两个或多个时钟信号源中的哪一个是当前正在使用的当前时钟信号源作为系统时钟信号源。 控制器的状态机逻辑自动切换，响应于时钟切换信号，系统时钟信号源从当前时钟信号源到两个或更多个时钟信号源的新时钟信号源。

公开(公告)号：US5828251A

公开(公告)日：1998-10-27

申请号：US674411

申请日：1996-07-02

申请人： Ronald Lamar Freyman ,  Michael James Hunter

发明人： Ronald Lamar Freyman ,  Michael James Hunter

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions. In a preferred embodiment, the second capacitor is effectively disabled at low power supply voltages. This facilitates conduction of the discharge transistor for power supply voltage interruptions resulting from slow changes (low slew rate) in the power supply voltage.

摘要翻译： 集成电路包括上电检测器电路，其包括在正常操作期间由电容器保持在充电状态的节点。 节点上的电压由感测电路感测，通常是在最初施加电力时产生上电复位脉冲的逆变器。 然而，在短暂的电源中断期间，节点上的电压在所有情况下可能无法正确放电。 因此，为了提高上电检测器的可靠性，包括放电电路以帮助确保当电源电压降低到给定电平以下时，由电源电压感测电路感测到的电压处于适当的电平。 放电电路包括当电源电压低于给定电平时接通节点放电晶体管的第一电容器。 为了提供防止假放电的保护，可选地提供第二电容器，其在非常短暂的电源电压中断期间防止放电晶体管导通。 在优选实施例中，第二电容器在低电源电压下被有效地禁用。 这有助于放电晶体管的导通，导致电源电压缓慢变化（低压摆率）导致的电源电压中断。

公开(公告)号：US08218770B2

公开(公告)日：2012-07-10

申请号：US11539327

申请日：2006-10-06

申请人： Ambalavanar Arulambalam ,  David E. Clune ,  Nevin C. Heintze ,  Michael James Hunter ,  Hakan I. Pekcan

发明人： Ambalavanar Arulambalam ,  David E. Clune ,  Nevin C. Heintze ,  Michael James Hunter ,  Hakan I. Pekcan

IPC分类号： H04L29/06

CPC分类号： G06F21/72 ,  H04L9/0894 ,  H04L2209/603

摘要： Described embodiments provide a server for transferring data packets of streaming data sessions between devices. The server includes an accelerator that, for received data packets, i) extracts header fields of the packets, ii) determines, based on the header fields, a destination for the packets, and iii) provides the packets to the destination. For data to be transmitted, the accelerator i) groups the data into packets, ii) generates header fields for the packets, and iii) provides the packets to the network. A memory arbiter manages accesses to memory that buffers data and stores keys corresponding to the data sessions. A storage medium stores media files corresponding to the data sessions. A key manager includes i) a first memory for storing a master key of the server, ii) a second memory for storing one or more keys corresponding to the data sessions, and iii) a processor to encrypt and decrypt data.

摘要翻译： 所描述的实施例提供了一种用于在设备之间传送流数据会话的数据分组的服务器。 服务器包括加速器，对于接收的数据分组，i）提取分组的报头字段，ii）基于报头字段确定分组的目的地，以及iii）向目的地提供分组。 对于要发送的数据，加速器i）将数据分组成分组，ii）产生分组的报头字段，以及iii）向网络提供分组。 内存仲裁器管理对存储器的访问，缓冲数据并存储对应于数据会话的密钥。 存储介质存储对应于数据会话的媒体文件。 密钥管理器包括：i）用于存储服务器的主密钥的第一存储器，ii）用于存储与数据会话相对应的一个或多个密钥的第二存储器，以及iii）加密和解密数据的处理器。

公开(公告)号：US20190150507A1

公开(公告)日：2019-05-23

申请号：US15817626

申请日：2017-11-20

申请人： Michael James Hunter

发明人： Michael James Hunter

IPC分类号： A24F47/00 ,  H01R24/00 ,  H01R13/625

摘要： An electronic cigarette apparatus including a first and second modules; the first removably connected to the second; wherein the first module includes a male connector, a tank, and an upper portion; wherein the second module includes a lower portion which removably connects to the upper portion of the first module to removably connect the first and second modules; and wherein the second module further includes a female connector and a battery device. The lower portion may include a top section having at least two tabs; and wherein the upper portion includes at least two slots into which the at least two tabs of the lower portion can be inserted to connect the upper and lower portions. The upper portion may include one or more ledges which assist in preventing the lower and upper portions from disconnecting, unless the upper portion is rotated with respect to the lower portion.

公开(公告)号：US06834318B2

公开(公告)日：2004-12-21

申请号：US09785653

申请日：2001-02-16

申请人： Michael James Hunter ,  Hyun Lee ,  David Wayne Potter

发明人： Michael James Hunter ,  Hyun Lee ,  David Wayne Potter

IPC分类号： G06F1300

CPC分类号： G06F13/4045

摘要： A bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer block. The buffer block contains one pair of buffers for each bus bit and an extra pair associated with the indicator lines. Indicator lines are used by the direction control block based on activity on the bus to generate control signals (control-A and control-B) that control the state of the tri-state buffers. In an exemplary embodiment, each node must toggle the indicator line whenever the node drives the bus. When the bus is inactive, the control-A and control-B signals generated by the direction control block are both inactive because the voltages on both sides of the bidirectional bus repeater are the same. When the direction control block detects a change of voltage on the indicator line associated with one side of the bus (e.g., indicator-A associated with bus-A), the corresponding tri-state buffers are enabled. Thereafter, the opposite bus segment (bus-B) is driven by the repeater buffers, until the bus segment bus-B reaches the same logic level as the bus segment bus-A. The logic level on indicator-B also changes to the same logic level as indicator-A. Eventually, both segments of the bus wire and the indicator wires connected to the bidirectional bus repeater circuit are equal and the DC turns off the a control signal A (cntl-A).

摘要翻译： 公开了连接双向总线的各个段的双向总线中继器。 示例性双向总线中继器由方向控制块和缓冲块组成。 缓冲区块包含一对缓冲区，用于每个总线位和与指示线相关联的额外的一对。 指示线由方向控制块根据总线上的活动使用，以产生控制三态缓冲器状态的控制信号（控制A和控制B）。 在示例性实施例中，每当节点驱动总线时，每个节点必须切换指示线。 当总线无效时，由方向控制块产生的控制A和控制B信号都是无效的，因为双向总线中继器两侧的电压相同。 当方向控制块检测到与总线一侧相关联的指示线上的电压变化（例如，与总线A相关联的指示符-A）时，相应的三态缓冲器被使能。 此后，相反的总线段（总线B）由中继器缓冲器驱动，直到总线段总线-B达到与总线段总线A相同的逻辑电平。 指标-B上的逻辑电平也变为与指标-A相同的逻辑电平。 最终，总线的两段和连接到双向总线中继器电路的指示线相同，并且DC关断控制信号A（cntl-A）。