公开(公告)号：US06240487B1

公开(公告)日：2001-05-29

申请号：US09025606

申请日：1998-02-18

申请人： Pei-Chun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Stephen Tung ,  Dwain Alan Hicks ,  Kin Shing Chan

发明人： Pei-Chun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Stephen Tung ,  Dwain Alan Hicks ,  Kin Shing Chan

IPC分类号： G06F1208

CPC分类号： G06F12/0859 ,  G06F12/0851

摘要： A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.

摘要翻译： 高速缓存具有用于保存数据或指令值的阵列，连接到该阵列的缓冲器，以及用于访问缓冲器以检索处理单元的值的装置。 访问装置使用具有基本上等于高速缓存阵列的线间距的间距的线。 多路复用器可以与多个这样的缓冲器一起使用以创建公共输出路径。 高速缓存可以被交织，阵列是第一子阵列，缓冲器是第一缓冲器，并且还包括第二子阵列和第二缓冲器，其中第一和第二缓冲器分离第一和第二子阵列。 本发明可以应用于存储缓冲器以及重新加载缓冲器。

公开(公告)号：US5682495A

公开(公告)日：1997-10-28

申请号：US353007

申请日：1994-12-09

申请人： Brad B. Beavers ,  Lew Chua-Eoan ,  Pei-Chun Peter Liu ,  Chih-Jui Peng

发明人： Brad B. Beavers ,  Lew Chua-Eoan ,  Pei-Chun Peter Liu ,  Chih-Jui Peng

IPC分类号： G06F12/10

CPC分类号： G06F12/1036

摘要： A fully associative address translator which includes a number of entries, each of said number of entries translating a received effective address into a real address, each received effective address including a segment identifier and a page identifier. Each of the entries within the fully associative address translator includes a first translation from an effective address segment identifier into a virtual address segment identifier and a second translation from a virtual address page identifier to a real address page identifier. A first valid bit cell is provided for storing a validity bit which indicates the validity of the first translation from the effective address segment identifier to the virtual address segment identifier and a second valid bit cell is also provided for storing a validity bit indicating the validity of the second translation from the virtual address page identifier to the real address page identifier wherein a process context switch will invalidate only a portion of each of the entries, thereby reducing the miss penalty associated with a context switch.

摘要翻译： 一种完全关联地址转换器，其包括多个条目，所述数量的条目中的每一个将接收的有效地址转换为实际地址，每个接收到的有效地址包括段标识符和页面标识符。 完全关联地址转译器中的每个条目包括从有效地址段标识符到虚拟地址段标识符的第一转换和从虚拟地址页标识符到真实地址页标识符的第二转换。 提供第一有效比特单元，用于存储指示从有效地址段标识符到虚拟地址段标识符的第一翻译的有效性的有效位，并且还提供第二有效位单元，用于存储指示有效位的有效位 从虚拟地址页标识符到实际地址页标识符的第二转换，其中处理上下文切换将仅使每个条目的一部分无效，从而减少与上下文切换相关联的未命中。