公开(公告)号：US5937429A

公开(公告)日：1999-08-10

申请号：US844550

申请日：1997-04-21

申请人： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

发明人： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

IPC分类号： G06F12/12

CPC分类号： G06F12/127

摘要： A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

摘要翻译： 描述了具有可选择的高速缓存线更换方案的高速缓冲存储器。 根据本发明的优选实施例，高速缓冲存储器具有多个高速缓存线，多个令牌寄存器，令牌和选择电路。 令牌寄存器以环形配置相互连接。 存在相等数量的令牌寄存器和高速缓存行，并且每个令牌寄存器与其中一个高速缓存行相关联。 令牌被用于将一个缓存行指示为由令牌结算的相关联的令牌寄存器替换的候选。 选择电路与所有令牌寄存器相关联。 该选择电路提供至少两种方法来控制令牌在令牌寄存器的环内的移动，以便在运行时期间可选择。 令牌移动的每种方法代表高速缓存行替换方案。

公开(公告)号：US5905999A

公开(公告)日：1999-05-18

申请号：US638661

申请日：1996-04-29

申请人： Peichun Peter Liu ,  Salim Ahmed Shah ,  Rajinder Paul Singh

发明人： Peichun Peter Liu ,  Salim Ahmed Shah ,  Rajinder Paul Singh

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0851

摘要： A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses corresponding to memory locations in the cache, and determines in which sub-arrays the memory locations reside. If the two memory locations reside in the same sub-array, the arbitration circuit sends the higher priority address to the sub-array. If a received address operand is the real address of a cache miss, the arbitration circuit sends the cache miss address to the sub-array before other pre-fetch memory access request.

摘要翻译： 一种高速缓存子阵列仲裁电路，用于从未决的处理器指令行接收多个地址操作数，以便预取在未决指令中的任何存储器访问请求中所需的数据。 子阵列仲裁电路将至少两个对应于高速缓存中的存储器位置的地址进行比较，并确定存储器位置在哪个子阵列中。 如果两个存储器位置位于相同的子阵列中，则仲裁电路将较高优先级地址发送到子阵列。 如果接收到的地址操作数是高速缓存未命中的真实地址，则仲裁电路在其他预取存储器访问请求之前将高速缓存未命中地址发送到子阵列。

公开(公告)号：US5787478A

公开(公告)日：1998-07-28

申请号：US810775

申请日：1997-03-05

申请人： Dwain Alan Hicks ,  Peichun Peter Liu ,  Michael John Mayfield ,  Rajinder Paul Singh

发明人： Dwain Alan Hicks ,  Peichun Peter Liu ,  Michael John Mayfield ,  Rajinder Paul Singh

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811

摘要： A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.

摘要翻译： 公开了一种实现用于在数据处理系统内支持非包容性高速缓存存储器层级的高速缓存一致性机制的方法和系统。 根据本发明的方法和系统，存储器层级包括主高速缓冲存储器，副高速缓冲存储器和主存储器。 主缓冲存储器和次高速缓冲存储器是不包含的。 此外，与主缓存器的每个高速缓存行相关联地，在主缓存器内提供第一状态位和第二状态位。 作为优选实施例，仅当在一级高速缓冲存储器中的对应的高速缓存行已经在直写模式下被修改时才设置第一状态位，而仅当相应的高速缓存行也存在于次级 高速缓存存储器。 这样，可以通过利用主高速缓存存储器中的第一状态位和第二状态位来维持主高速缓存存储器和辅助高速缓冲存储器之间的高速缓存一致性。

公开(公告)号：US6041390A

公开(公告)日：2000-03-21

申请号：US773545

申请日：1996-12-23

申请人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

发明人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

IPC分类号： G06F12/12

CPC分类号： G06F12/121

摘要： A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated. Each token register also has a bypass circuit. A bypass circuit is utilized to transfer the token from one token register to an adjacent token circuit in response to an indication from the associated allocation-indicating circuit.

摘要翻译： 公开了一种用于具有冗余高速缓存行的高速缓冲存储器内的高速缓存行替换机制。 根据本发明的优选实施例，该机制包括令牌，多个令牌寄存器，多个分配指示电路，多个旁路电路，以及用于响应于位置替换高速缓冲存储器内的高速缓存行的电路 的令牌。 顺便提及，该令牌用于指示用于高速缓存行替换的候选高速缓存行。 令牌寄存器以环形配置连接，并且每个令牌寄存器与高速缓冲存储器的高速缓存行相关联，包括所有冗余高速缓存行。 通常，这些令牌寄存器之一包含令牌。 每个令牌寄存器具有分配指示电路。 分配指示电路用于指示与分配指示电路相关联的高速缓存行是否正在进行分配过程。 每个令牌寄存器还具有旁路电路。 响应于来自相关联的分配指示电路的指示，利用旁路电路将令牌从一个令牌寄存器传送到相邻令牌电路。

公开(公告)号：US5802567A

公开(公告)日：1998-09-01

申请号：US742233

申请日：1996-10-31

申请人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

发明人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/1054 ,  G06F12/0864

摘要： A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory circuit, a second directory circuit, a multiple number of most recently used bits, and a multiple number of set/reset circuits. The first directory circuit, having multiple caches lines, is utilized to receive partial effective addresses. The second directory circuit is utilized to receive an output from the first directory circuit. A most recently used bit is associated with each cache line within the first directory circuit. The set/reset circuit, coupled to each of the most recently used bits, is utilized to set one of the most recently used bits to a first state while concurrently resetting the rest of the most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing conditions such that offset or aliasing conditions can be more efficiently managed.

摘要翻译： 公开了一种具有用于管理偏移和混叠条件的机制的高速缓冲存储器。 根据本发明的优选实施例，高速缓冲存储器包括第一目录电路，第二目录电路，多个最近使用的位以及多个设置/复位电路。 具有多个高速缓存行的第一目录电路被用于接收部分有效地址。 第二目录电路用于接收来自第一目录电路的输出。 最近使用的位与第一目录电路内的每个高速缓存行相关联。 耦合到每个最近使用的位的置位/复位电路用于将最近使用的位之一设置为第一状态，同时将单个周期内的最近使用的位的其余部分复位到第二状态 在偏移或混叠条件的发生期间，可以更有效地管理偏移或混叠条件。

公开(公告)号：US5761714A

公开(公告)日：1998-06-02

申请号：US638263

申请日：1996-04-26

申请人： Peichun Peter Liu ,  Rajinder Paul Singh

发明人： Peichun Peter Liu ,  Rajinder Paul Singh

IPC分类号： G06F12/06 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0851

摘要： An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.

摘要翻译： 公开了一种具有单周期多路访问能力的交错缓存。 交错缓存存储器包括存储单元的多个子阵列，用于接收这些子阵列的多个输入地址的仲裁逻辑电路，以及用于将这些多个输入地址应用于这些子阵列的地址输入电路。 这些子阵列中的每一个包括偶数数据部分和奇数数据部分和三个内容可寻址存储器，用于接收多个输入地址以便与存储在这三个可内容寻址存储器中的标签进行比较。 三个可内容寻址存储器中的第一个与偶数据部分相关联，并且三个可内容寻址存储器中的第二个与奇数据部分相关联。 如果多个输入地址尝试访问相同子阵列的相同数据段，则仲裁逻辑电路然后用于选择多个输入地址中的一个进行进行。

公开(公告)号：US06814487B2

公开(公告)日：2004-11-09

申请号：US10371543

申请日：2003-02-20

申请人： Rajinder Paul Singh ,  Jane Kee Kim ,  Linh My Dang

发明人： Rajinder Paul Singh ,  Jane Kee Kim ,  Linh My Dang

IPC分类号： G01K1300

CPC分类号： G01K1/146 ,  G01K2207/06

摘要： An apparatus for measuring internal temperatures of food patties that includes a drawer sled slidably mounted on a pair of shafts. The drawer sled is formed with a drawer cavity that is sized and shaped to receive a food patty. Moreover, the drawer sled is movable between a loading/unloading position and a temperature measuring position. In the loading/unloading position a food patty can be inserted into or removed from the drawer cavity. Conversely, in the temperature measuring position, one or more temperature probes are inserted radially into the food patty such that one of the temperature probes detects the temperature of the food patty at its geometric center.

摘要翻译： 一种用于测量食物的内部温度的装置，包括可滑动地安装在一对轴上的抽屉滑动件。 抽屉雪橇形成有一个抽屉腔，其尺寸和形状可以容纳食物箱。 此外，抽屉滑轨可在装载/卸载位置和温度测量位置之间移动。 在装载/卸载位置，可以将食品馅饼插入或从抽屉腔中移出。 相反，在温度测量位置，将一个或多个温度探针径向地插入食物盒中，使得一个温度探针在其几何中心处检测食物馅饼的温度。

公开(公告)号：US06304939B1

公开(公告)日：2001-10-16

申请号：US09404036

申请日：1999-09-23

申请人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

发明人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

IPC分类号： G06F1212

CPC分类号： G06F12/121

摘要： A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated. Each token register also has a bypass circuit. A bypass circuit is utilized to transfer the token from one token register to an adjacent token circuit in response to an indication from the associated allocation-indicating circuit.

摘要翻译： 公开了一种用于具有冗余高速缓存线的高速缓冲存储器内的高速缓存行替换的机制。 根据本发明的优选实施例，该机制包括令牌，多个令牌寄存器，多个分配指示电路，多个旁路电路，以及用于响应于位置替换高速缓冲存储器内的高速缓存行的电路 的令牌。 顺便提及，该令牌用于指示用于高速缓存行替换的候选高速缓存行。 令牌寄存器以环形配置连接，并且每个令牌寄存器与高速缓冲存储器的高速缓存行相关联，包括所有冗余高速缓存行。 通常，这些令牌寄存器之一包含令牌。 每个令牌寄存器具有分配指示电路。 分配指示电路用于指示与分配指示电路相关联的高速缓存行是否正在进行分配过程。 每个令牌寄存器还具有旁路电路。 响应于来自相关联的分配指示电路的指示，利用旁路电路将令牌从一个令牌寄存器传送到相邻令牌电路。

公开(公告)号：US06240487B1

公开(公告)日：2001-05-29

申请号：US09025606

申请日：1998-02-18

申请人： Pei-Chun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Stephen Tung ,  Dwain Alan Hicks ,  Kin Shing Chan

发明人： Pei-Chun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Stephen Tung ,  Dwain Alan Hicks ,  Kin Shing Chan

IPC分类号： G06F1208

CPC分类号： G06F12/0859 ,  G06F12/0851

摘要： A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.

摘要翻译： 高速缓存具有用于保存数据或指令值的阵列，连接到该阵列的缓冲器，以及用于访问缓冲器以检索处理单元的值的装置。 访问装置使用具有基本上等于高速缓存阵列的线间距的间距的线。 多路复用器可以与多个这样的缓冲器一起使用以创建公共输出路径。 高速缓存可以被交织，阵列是第一子阵列，缓冲器是第一缓冲器，并且还包括第二子阵列和第二缓冲器，其中第一和第二缓冲器分离第一和第二子阵列。 本发明可以应用于存储缓冲器以及重新加载缓冲器。

公开(公告)号：US6064245A

公开(公告)日：2000-05-16

申请号：US26087

申请日：1998-02-19

申请人： Rajinder Paul Singh ,  Pei-Chun Liu ,  Song Kim

发明人： Rajinder Paul Singh ,  Pei-Chun Liu ,  Song Kim

IPC分类号： H03K3/356 ,  H03K3/027

CPC分类号： H03K3/356139

摘要： The present invention is directed to an apparatus for precharging complementary data circuits. The apparatus comprises two hold circuits, one for storing the data and the other for storing its complement. A signal for initiates precharging the hold circuits to the same signal level, where the signal for initiating the precharging of the hold circuits is dependent on the hold circuits' outputs.

摘要翻译： 本发明涉及一种用于对互补数据电路进行预充电的装置。 该装置包括两个保持电路，一个用于存储数据，另一个用于存储其补码。 用于启动将保持电路预充电到相同信号电平的信号，其中用于启动保持电路的预充电的信号取决于保持电路的输出。