公开(公告)号：US06509725B1

公开(公告)日：2003-01-21

申请号：US09683025

申请日：2001-11-09

申请人： Kerry Bernstein ,  Peter Edwin Cottrell ,  Roger Paul Gregor ,  Stephen V. Kosonocky ,  Edward Joseph Nowak

发明人： Kerry Bernstein ,  Peter Edwin Cottrell ,  Roger Paul Gregor ,  Stephen V. Kosonocky ,  Edward Joseph Nowak

IPC分类号： G05F304

CPC分类号： G06F1/26

摘要： A system and method for achieving self-regulated voltage division among multiple serially stacked voltage planes. The system of the present invention is incorporated within a source voltage plane having a source supply node for supplying current and a source ground node for sinking current supplied therefrom. An intermediate voltage supply node is coupled between the source supply voltage node and the source ground node for dividing the source voltage plane into a plurality of intermediate voltage planes. The self-regulated voltage divider of the present invention includes a first capacitor and a second capacitor that are each controllably coupled between either the source supply voltage node and the intermediate voltage supply node, or between the intermediate voltage supply node and the source ground node, such that a voltage level balance is achieved among the intermediate voltage planes.

摘要翻译： 一种用于在多个串联电压平面之间实现自调节电压分配的系统和方法。 本发明的系统结合在具有用于提供电流的源电源节点的源极电压平面和用于吸收从其提供的电流的源极接地节点。 中间电压供应节点耦合在源电源电压节点和源极接地节点之间，用于将源极电压平面分成多个中间电压平面。 本发明的自调节分压器包括第一电容器和第二电容器，每个可控制地耦合在源电源电压节点和中间电压供应节点之间，或者在中间电压供应节点和源极接地节点之间， 使得在中间电压平面之间实现电压电平平衡。

公开(公告)号：US06605981B2

公开(公告)日：2003-08-12

申请号：US09842544

申请日：2001-04-26

申请人： Andres Bryant ,  Peter Edwin Cottrell ,  John Joseph Ellis-Monaghan ,  Mark B. Ketchen ,  Edward Joseph Nowak

发明人： Andres Bryant ,  Peter Edwin Cottrell ,  John Joseph Ellis-Monaghan ,  Mark B. Ketchen ,  Edward Joseph Nowak

IPC分类号： G05F302

CPC分类号： G05F3/205 ,  H01L27/0218

摘要： An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.