公开(公告)号：US857877A

公开(公告)日：1907-06-25

申请号：US1907353736

申请日：1907-01-23

Applicant: FETTER RALPH SNOWDEN

Inventor： FETTER RALPH SNOWDEN

CPC classification number: H01R43/058

公开(公告)号：US07274660B2

公开(公告)日：2007-09-25

申请号：US10222733

申请日：2002-08-15

Applicant: Charles Hill ,  Rajesh Mangal ,  Ralph Snowden ,  Harold K. Williamson ,  James Holbrook

Inventor： Charles Hill ,  Rajesh Mangal ,  Ralph Snowden ,  Harold K. Williamson ,  James Holbrook

IPC: H04L12/26 ,  H04J1/16 ,  G08C15/00 ,  G06F11/00 ,  G01R31/08

CPC classification number: H04L49/508 ,  H04L47/10 ,  H04L47/11 ,  H04L47/12 ,  H04L47/22 ,  H04L49/10 ,  H04L49/30 ,  H04L49/50

Abstract: Flow control in a distributed switch fabric (100, 200) includes detecting at least one of a congestion condition (238) in a downstream transceiver port (205) and an oversubscribing condition (257) of a channel buffer (230), where the downstream transceiver port (205) and the channel buffer (230) both correspond to a channel (231) of a traffic manager (208). Packets begin accumulating in the channel buffer (230). Per-flow flow control (254) operates to modify transmission of the packets over the channel (231) to the channel buffer (230) if the channel buffer (230) reaches a threshold value (256). Link level flow control (252) operates transparently to the traffic manager (208) if the congestion condition (238) is detected and the channel buffer (230) fails to reach the threshold value (256).

Abstract translation: 分布式交换结构（100,200）中的流控制包括检测下游收发器端口（205）中的拥塞状况（238）和信道缓冲器（230）的超额订购条件（257）中的至少一个，其中下游 收发器端口（205）和信道缓冲器（230）都对应于业务管理器（208）的信道（231）。 分组开始在通道缓冲器（230）中累积。 如果信道缓冲器（230）达到阈值（256），则每流量流控制（254）操作以修改通道（231）上的分组到信道缓冲器（230）的传输。 如果检测到拥塞状况（238）并且信道缓冲器（230）未达到阈值（256），则链路级流量控制（252）对流量管理器（208）透明地操作。

公开(公告)号：US5825706A

公开(公告)日：1998-10-20

申请号：US958645

申请日：1997-10-27

Applicant: Ralph Snowden ,  Wendy Reed ,  Glen James Zoerner ,  Wai-Kin Steven Kwan ,  On Ki Andrew Chu ,  Hing Leung Yiu

Inventor： Ralph Snowden ,  Wendy Reed ,  Glen James Zoerner ,  Wai-Kin Steven Kwan ,  On Ki Andrew Chu ,  Hing Leung Yiu

IPC: G06F1/24 ,  G06F12/00 ,  G11C11/406 ,  G11C7/00

CPC classification number: G11C11/406

Abstract: When an external reset signal EXRST is asserted received by a reset unit (6), it is synchronised with an internal clock to produce an internal reset signal INRST, which is applied to a CPU (4) and other modules in the circuit to reset them. While the internal reset signal INRST is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller (7) for refreshing data in DRAM (3) is increased. Then, when the external reset signal EXRST is disabled, a delayed reset signal DLYRST is generated and applied to the DRAM controller (7) so that it is reset. The CPU, being already reset, can then quickly reconfigure the DRAM controller and re-enable it to resume refreshing the DRAM (4), thus maintaining the data in the DRAM.

Abstract translation: 当由复位单元（6）接收到外部复位信号EXRST时，它与内部时钟同步，产生内部复位信号INRST，该内部复位信号INRST被施加到电路中的CPU（4）和其他模块以复位它们 。 当内部复位信号INRST被施加到CPU时，由用于刷新DRAM（3）中的数据的DRAM控制器（7）产生的刷新信号的速率增加。 然后，当外部复位信号EXRST被禁止时，生成延迟的复位信号DLYRST并将其施加到DRAM控制器（7），使得其被复位。 已经重置的CPU可以快速重新配置DRAM控制器，并重新启用它来恢复刷新DRAM（4），从而将数据保留在DRAM中。