Efficient semiconductor burn-in circuit and method of operation
    1.
    发明授权
    Efficient semiconductor burn-in circuit and method of operation 失效
    高效半导体老化电路及其操作方法

    公开(公告)号:US6038181A

    公开(公告)日:2000-03-14

    申请号:US136112

    申请日:1998-08-18

    IPC分类号: G11C29/00 G01R31/30 G11C7/00

    CPC分类号: G01R31/30

    摘要: The disclosed invention provides a circuit and burn-in test method for semiconductor devices that increases the speed of burn-in tests. The present invention accomplishes this by causing each of the devices under test to be tested multiple times (from 2 to 32+ times) during each power cycle. By such multiple cycling of the unit under test, during the power cycle, the total test time is shortened. It has also been found that the devices tested in accordance with the present invention are more efficiently stressed and have a reliability greater than devices passing the prior art tests. In accordance with the invention, the memory or logic devices under test are provided with a respective clock means that will operate each of the devices under test through multiple (from 2 to 32+ times) write and read operations during each power cycle. Data coherency for each read operation is provided as is the inversion of data if any fail is recorded during a read operation. Accordingly, the present invention provides a burn-in test that more efficiently stresses semiconductor devices such as memory or logic units, by a factor of up to 32. The invention utilizes the internal clock of a semiconductor device by cycling that clock x times during the period of each external clock cycle in the burn-in test and simultaneously synchronizes these internal cycles with the test cycle, thereby providing coherent data for each internal cycle.

    摘要翻译: 所公开的发明提供了一种提高老化测试速度的半导体器件的电路和老化测试方法。 本发明通过在每个功率循环期间使被测设备中的每一个被测试多次(从2到32倍)来实现。 通过被测单元的这种多次循环,在电源循环期间,总测试时间缩短。 还已经发现,根据本发明测试的装置被更有效地应力并且具有比通过现有技术测试的装置更大的可靠性。 根据本发明,被测试的存储器或逻辑器件设置有相应的时钟装置,其将在每个功率循环期间通过多次(从2到32+倍)的写入和读取操作来操作被测试的每个器件。 如果在读取操作期间记录任何失败,则提供每个读取操作的数据一致性。 因此,本发明提供了一种老化测试,其更有效地将半导体器件(例如存储器或逻辑单元)应力高达32倍。本发明通过在半导体器件的周期内循环该时钟x次来利用半导体器件的内部时钟 在老化测试中每个外部时钟周期的周期,同时使这些内部周期与测试周期同步,从而为每个内部循环提供相干数据。