公开(公告)号：US20110176078A1

公开(公告)日：2011-07-21

申请号：US13074126

申请日：2011-03-29

申请人： In-Woo KIM ,  Sun-Ok SONG

发明人： In-Woo KIM ,  Sun-Ok SONG

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/133707

摘要： An array substrate includes a switching device, a storage capacitor and a voltage-dividing capacitor. The switching device is formed in a pixel region defined by two gate lines adjacent to each other and two data lines adjacent to each other. The storage capacitor is electrically connected to the switching device. The voltage-dividing capacitor is disposed between the storage capacitor and one of the gate lines. The voltage-dividing capacitor is electrically connected to the storage capacitor. Therefore, an overlapping area with the data lines is reduced to reduce the RC delay and enhance aperture ratio. Furthermore, a possibility of occurrence of an electrical short is reduced.

摘要翻译： 阵列基板包括开关装置，存储电容器和分压电容器。 开关器件形成在由彼此相邻的两个栅极线和彼此相邻的两个数据线限定的像素区域中。 存储电容器电连接到开关装置。 分压电容器设置在存储电容器和其中一条栅极线之间。 分压电容器电连接到存储电容器。 因此，减少与数据线的重叠区域以减少RC延迟并增加开口率。 此外，电短路发生的可能性降低。

公开(公告)号：US20060189054A1

公开(公告)日：2006-08-24

申请号：US11346717

申请日：2006-02-03

申请人： Beom-Jun Kim ,  Sun-Ok Song ,  Myung-Koo Hur

发明人： Beom-Jun Kim ,  Sun-Ok Song ,  Myung-Koo Hur

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/41733 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458

摘要： A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a data line including a source electrode and a drain electrode on the ohmic contact layer. The method further includes depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode, depositing a passivation layer, and removing the first photoresist to form a passivation member.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法包括：在衬底上形成包括栅电极的栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在该栅极绝缘层上形成欧姆接触层 半导体层，并且在欧姆接触层上形成包括源电极和漏电极的数据线。 该方法还包括在数据线和漏电极上沉积导电膜，在导电膜上形成第一光致抗蚀剂，使用第一光致抗蚀剂作为掩模蚀刻导电膜，以形成至少连接到漏电极的像素电极， 沉积钝化层，并除去第一光致抗蚀剂以形成钝化部件。

公开(公告)号：US07846784B2

公开(公告)日：2010-12-07

申请号：US11346717

申请日：2006-02-03

申请人： Beom-Jun Kim ,  Sun-Ok Song ,  Myung-Koo Hur

发明人： Beom-Jun Kim ,  Sun-Ok Song ,  Myung-Koo Hur

IPC分类号： H01L21/00

CPC分类号： H01L29/41733 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458

摘要： A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a data line including a source electrode and a drain electrode on the ohmic contact layer. The method further includes depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode, depositing a passivation layer, and removing the first photoresist to form a passivation member.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法包括：在衬底上形成包括栅电极的栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在该栅极绝缘层上形成欧姆接触层 半导体层，并且在欧姆接触层上形成包括源电极和漏电极的数据线。 该方法还包括在数据线和漏电极上沉积导电膜，在导电膜上形成第一光致抗蚀剂，使用第一光致抗蚀剂作为掩模蚀刻导电膜，以形成至少连接到漏电极的像素电极， 沉积钝化层，并除去第一光致抗蚀剂以形成钝化部件。

公开(公告)号：US20060187368A1

公开(公告)日：2006-08-24

申请号：US11353272

申请日：2006-02-14

申请人： In-Woo Kim ,  Sun-Ok Song

发明人： In-Woo Kim ,  Sun-Ok Song

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/133707

摘要： An array substrate includes a switching device, a storage capacitor and a voltage-dividing capacitor. The switching device is formed in a pixel region defined by two gate lines adjacent to each other and two data lines adjacent to each other. The storage capacitor is electrically connected to the switching device. The voltage-dividing capacitor is disposed between the storage capacitor and one of the gate lines. The voltage-dividing capacitor is electrically connected to the storage capacitor. Therefore, an overlapping area with the data lines is reduced to reduce the RC delay and enhance aperture ratio. Furthermore, a possibility of occurrence of an electrical short is reduced.

公开(公告)号：US08525964B2

公开(公告)日：2013-09-03

申请号：US13074126

申请日：2011-03-29

申请人： In-Woo Kim ,  Sun-Ok Song

发明人： In-Woo Kim ,  Sun-Ok Song

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/133707

摘要： An array substrate includes a switching device, a storage capacitor and a voltage-dividing capacitor. The switching device is formed in a pixel region defined by two gate lines adjacent to each other and two data lines adjacent to each other. The storage capacitor is electrically connected to the switching device. The voltage-dividing capacitor is disposed between the storage capacitor and one of the gate lines. The voltage-dividing capacitor is electrically connected to the storage capacitor. Therefore, an overlapping area with the data lines is reduced to reduce the RC delay and enhance aperture ratio. Furthermore, a possibility of occurrence of an electrical short is reduced.

摘要翻译： 阵列基板包括开关装置，存储电容器和分压电容器。 开关器件形成在由彼此相邻的两个栅极线和彼此相邻的两个数据线限定的像素区域中。 存储电容器电连接到开关装置。 分压电容器设置在存储电容器和其中一条栅极线之间。 分压电容器电连接到存储电容器。 因此，减少与数据线的重叠区域以减少RC延迟并增加开口率。 此外，电短路发生的可能性降低。

公开(公告)号：US07936407B2

公开(公告)日：2011-05-03

申请号：US11353272

申请日：2006-02-14

申请人： In-Woo Kim ,  Sun-Ok Song

发明人： In-Woo Kim ,  Sun-Ok Song

IPC分类号： G02F1/1343 ,  G02F1/1337

CPC分类号： G02F1/136213 ,  G02F1/133707

摘要： An array substrate includes a switching device, a storage capacitor and a voltage-dividing capacitor. The switching device is formed in a pixel region defined by two gate lines adjacent to each other and two data lines adjacent to each other. The storage capacitor is electrically connected to the switching device. The voltage-dividing capacitor is disposed between the storage capacitor and one of the gate lines. The voltage-dividing capacitor is electrically connected to the storage capacitor. Therefore, an overlapping area with the data lines is reduced to reduce the RC delay and enhance aperture ratio. Furthermore, a possibility of occurrence of an electrical short is reduced.

摘要翻译： 阵列基板包括开关装置，存储电容器和分压电容器。 开关器件形成在由彼此相邻的两个栅极线和彼此相邻的两个数据线限定的像素区域中。 存储电容器电连接到开关装置。 分压电容器设置在存储电容器和其中一条栅极线之间。 分压电容器电连接到存储电容器。 因此，减少与数据线的重叠区域以减少RC延迟并增加开口率。 此外，电短路发生的可能性降低。