公开(公告)号：US08464005B2

公开(公告)日：2013-06-11

申请号：US13464689

申请日：2012-05-04

Applicant: Warren K. Howlett ,  Christopher L. Lyles

Inventor： Warren K. Howlett ,  Christopher L. Lyles

IPC: G06F12/00

CPC classification number: G06F9/52

Abstract: Systems and methods for accessing common registers in a multi-core processor are disclosed. In an exemplary embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Abstract translation: 公开了用于访问多核处理器中的公共寄存器的系统和方法。 在示例性实施例中，方法可以包括将至少一个事务从核心域中的多个处理核心之一直接流向寄存器域。 该方法还可以包括重新组合寄存器域中的至少一个流传输事务以用于在公共寄存器处的数据访问操作。

公开(公告)号：US20120221831A1

公开(公告)日：2012-08-30

申请号：US13464689

申请日：2012-05-04

Applicant: Warren K. Howlett ,  Christopher L. Lyles

Inventor： Warren K. Howlett ,  Christopher L. Lyles

IPC: G06F15/76 ,  G06F9/02

CPC classification number: G06F9/52

Abstract: Systems and methods for accessing common registers in a multi-core processor are disclosed. In an exemplary embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Abstract translation: 公开了用于访问多核处理器中的公共寄存器的系统和方法。 在示例性实施例中，方法可以包括将至少一个事务从核心域中的多个处理核心之一直接流向寄存器域。 该方法还可以包括重新组合寄存器域中的至少一个流传输事务以用于在公共寄存器处的数据访问操作。

公开(公告)号：US08209492B2

公开(公告)日：2012-06-26

申请号：US11152305

申请日：2005-06-14

Applicant: Warren K. Howlett ,  Christopher L. Lyles

Inventor： Warren K. Howlett ,  Christopher L. Lyles

IPC: G06F12/00

CPC classification number: G06F9/52

Abstract: Systems and methods for accessing common registers in a multi-core processor are disclosed. In an embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Abstract translation: 公开了用于访问多核处理器中的公共寄存器的系统和方法。 在示例性实施例中，方法可以包括将至少一个事务从核心域中的多个处理核心之一直接流向寄存器域。 该方法还可以包括重新组合寄存器域中的至少一个流传输事务以用于在公共寄存器处的数据访问操作。

公开(公告)号：US06944807B2

公开(公告)日：2005-09-13

申请号：US10107291

申请日：2002-03-25

Applicant: J. Michael Hill ,  Jonathan E. Lachman ,  Warren K Howlett

Inventor： J. Michael Hill ,  Jonathan E. Lachman ,  Warren K Howlett

IPC: G11C29/00

CPC classification number: G11C29/88 ,  G11C15/00 ,  G11C29/883

Abstract: The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.

Abstract translation: 本发明提供一种用于仅使用可用片上高速缓存的一部分来获得全功能微处理器的电路和方法。 测试片上缓存的存储器子阵列以确定哪些子阵列是有效的。 在确定哪些子阵列是有效的之后，选择一组构成高速缓存的二进制分数的子阵列。 CPU被初始化以适应与所选子阵列的大小相对应的较小的地址空间。 最后，一组信号被编程为允许CPU访问所选择的子阵列。