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1.发明申请Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache 失效具有L1指令高速缓存和共享L2指令高速缓存的多个多线程处理器公开(公告)号：US20090089546A1
公开(公告)日：2009-04-02
申请号：US12313247
申请日：2008-11-18
IPC分类号： G06F9/30
CPC分类号： G06F12/0811 , G06F12/0842 , H04L69/12
摘要： In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
摘要翻译： 一般来说，一方面，本发明描述了一种处理器，其包括指令存储器，用于存储至少一个程序的至少一部分和耦合到共享指令存储器的多个引擎的指令。 引擎提供多个执行线程并且包括指令高速缓存以从指令存储器缓存至少一个程序的至少一部分的子集，其中引擎指令高速缓存的不同相应部分分配给引擎的不同相应引擎 线程。
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2.发明授权Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache 失效具有L1指令高速缓存和共享L2指令高速缓存的多个多线程处理器公开(公告)号：US08087024B2
公开(公告)日：2011-12-27
申请号：US12313247
申请日：2008-11-18
CPC分类号： G06F12/0811 , G06F12/0842 , H04L69/12
摘要： In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
摘要翻译： 一般来说，一方面，本发明描述了一种处理器，其包括指令存储器，用于存储至少一个程序的至少一部分和耦合到共享指令存储器的多个引擎的指令。 引擎提供多个执行线程并且包括指令高速缓存以从指令存储器缓存至少一个程序的至少一部分的子集，其中引擎指令高速缓存的不同相应部分分配给引擎的不同相应引擎 线程。
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公开(公告)号：US07536692B2
公开(公告)日：2009-05-19
申请号：US10704431
申请日：2003-11-06
CPC分类号： G06F12/0811 , G06F12/0842 , H04L69/12
摘要： In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
摘要翻译： 一般来说，一方面，本发明描述了一种处理器，其包括指令存储器，用于存储至少一个程序的至少一部分和耦合到共享指令存储器的多个引擎的指令。 引擎提供多个执行线程并且包括指令高速缓存以从指令存储器缓存至少一个程序的至少一部分的子集，其中引擎指令高速缓存的不同相应部分分配给引擎的不同相应引擎 线程。
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4.发明授权Processing element with next and previous neighbor registers for direct data transfer 失效处理元素具有下一个和前一个相邻寄存器，用于直接数据传输公开(公告)号：US07275145B2
公开(公告)日：2007-09-25
申请号：US10746564
申请日：2003-12-24
申请人： Sridhar Lakshmanamurthy , Prashant Chandra , Wilson Y. Liao , Jeen-Yuan Miin , Pun Yim , Chen-Chi Kuo , Jaroslaw J. Sydir
发明人： Sridhar Lakshmanamurthy , Prashant Chandra , Wilson Y. Liao , Jeen-Yuan Miin , Pun Yim , Chen-Chi Kuo , Jaroslaw J. Sydir
IPC分类号： G06F9/302
CPC分类号： G06F15/17
摘要： According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and (ii) a previous neighbor register to receive information directly from a next processing element in the series.
摘要翻译： 根据一些实施例，处理元件包括（i）下一个相邻寄存器，用于直接从一系列处理元件中的先前处理元件接收信息，以及（ii）先前的邻居寄存器，用于直接从下一个处理元件接收信息 该系列。
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