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公开(公告)号:US20150009050A1
公开(公告)日:2015-01-08
申请号:US14191556
申请日:2014-02-27
Applicant: ANALOG DEVICES, INC.
Inventor: Lewis F. Lahr , William J. Thomas , William Hooper
IPC: H03M5/12
CPC classification number: H03M5/12
Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.
Abstract translation: 在一个示例性实施例中,公开了一种信号处理器,其被配置为对时钟优先的零切换差分曼彻斯特编码数据流进行解码。 数据流没有本地时钟,组合和顺序逻辑都用于将流解码为时钟数据信号和可选的错误信号。 解码包括将输入数据流分离成中间数据信号,中间时钟信号和调理信号的解析器。 数据和误差发生器接收三个信号并输出时钟数据信号和时钟误差信号。
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公开(公告)号:US09059724B2
公开(公告)日:2015-06-16
申请号:US14191556
申请日:2014-02-27
Applicant: Analog Devices, Inc.
Inventor: Lewis F. Lahr , William J. Thomas , William Hooper
CPC classification number: H03M5/12
Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.
Abstract translation: 在一个示例性实施例中,公开了一种信号处理器,其被配置为对时钟优先的零切换差分曼彻斯特编码数据流进行解码。 数据流没有本地时钟,组合和顺序逻辑都用于将流解码为时钟数据信号和可选的错误信号。 解码包括将输入数据流分离成中间数据信号,中间时钟信号和调理信号的解析器。 数据和误差发生器接收三个信号并输出时钟数据信号和时钟误差信号。
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