公开(公告)号：US20150363318A1

公开(公告)日：2015-12-17

申请号：US14306162

申请日：2014-06-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： JOHN L. REDFORD ,  MICHAEL G. PERKINS

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0895 ,  Y02D10/13

Abstract: In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation.

Abstract translation: 在一个示例中，提供了一种系统和方法，用于基于由指定地址寄存器访问的最后方式（如果可用）来预测所请求的存储器地址最有可能保持在多路高速缓存中的方式。 如果不可用，则系统可以确定没有可用的最佳预测。 在这种情况下，读取每种方式，忽略多余的值，或者根据需要执行缓存填充。 在某些实施例中，只有加法运算的最低有效位的一部分用于基加 - 偏移寻址模式中的方式预测。 这使得能够在全宽加法完成之前进行判定，从而通过预测操作不会不必要地延长时钟周期长度。