公开(公告)号：US12124371B2

公开(公告)日：2024-10-22

申请号：US17214356

申请日：2021-03-26

申请人： Intel Corporation

发明人： Ruchira Sasanka ,  Rajat Agarwal

IPC分类号： G06F12/08 ,  G06F12/0815 ,  G06F12/0895

CPC分类号： G06F12/0815 ,  G06F12/0895 ,  G06F2212/608

摘要： An apparatus and method to reduce bandwidth and latency associated with probabilistic caches. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data, one or more of the cores to generate a request for a first cache line; a cache controller comprising cache lookup logic to determine a first way of a cache in which to search for the first cache line based on a first set of tag bits comprising one or more bits associated with the first cache line; the cache lookup logic to compare a second set of tag bits of the first cache line with a third set of tag bits of an existing cache line stored in the first way, wherein if the second set of tag bits and the third set of tag bits to not match, then the cache lookup logic to determine that the first cache line is not in the first way and to compare a fourth set of tag bits of the first cache line with a fifth set of tag bits of the existing cache line, wherein responsive to a match between the fourth set of tag bits and the fifth set of tag bits, the cache lookup logic to determine that the first cache line is stored in a second way and to responsively read the first cache line from the second way.

公开(公告)号：US20240296129A1

公开(公告)日：2024-09-05

申请号：US18659407

申请日：2024-05-09

申请人： Texas Instruments Incorporated

发明人： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC分类号： G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC分类号： G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/603 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

摘要： A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

公开(公告)号：US12079135B2

公开(公告)日：2024-09-03

申请号：US18209967

申请日：2023-06-14

申请人： Rambus Inc.

发明人： Frederick A. Ware

IPC分类号： G06F12/08 ,  G06F12/0802 ,  G06F12/0846 ,  G06F12/0895 ,  G06F12/1027 ,  G11C8/06

CPC分类号： G06F12/0895 ,  G06F12/0802 ,  G06F12/0851 ,  G06F12/1027 ,  G11C8/06 ,  G06F2212/1044

摘要： A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

公开(公告)号：US12061907B2

公开(公告)日：2024-08-13

申请号：US17704127

申请日：2022-03-25

申请人： NOKIA SOLUTIONS AND NETWORKS OY

发明人： Pranjal Kumar Dutta

IPC分类号： G06F9/30 ,  G06F12/0862 ,  G06F12/0895

CPC分类号： G06F9/30047 ,  G06F9/30145 ,  G06F12/0862 ,  G06F12/0895

摘要： Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments may be configured to support a micro-architecture for a micro-operations cache (UC) of a processor. Various example embodiments for supporting a micro-architecture for a UC of a processor may be configured to implement the UC of a processor using an intermediate vector UC (IV-UC). Various example embodiments for supporting an IV-UC for a processor may be configured to support a processor including an IV-UC where the IV-UC includes a micro-operations cache (UC) configured to store a cache line including sets of micro-operations (UOPs) from instructions decoded by the processor and an intermediate vector cache (IVC) configured to store indications of locations of the sets of UOPs in the cache line of the UC for intermediate instructions of the cache line of the UC.

公开(公告)号：US20240264974A1

公开(公告)日：2024-08-08

申请号：US18640044

申请日：2024-04-19

申请人： Ascenium, Inc.

发明人： Peter Foley

IPC分类号： G06F15/80 ,  G06F12/0895

CPC分类号： G06F15/8007 ,  G06F12/0895

摘要： Techniques for parallel processing based on hazard mitigation avoidance are disclosed. An array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operation hazard mitigation is enabled. The hazard mitigation is enabled by a control word tag. The control word tag supports memory access precedence information and is provided by the compiler at compile time. A hazardless memory access operation is executed. The hazardless memory access operation is determined by the compiler, and the hazardless memory access operation is designated by a unique set of precedence information contained in the tag. The tag is modified during runtime by hardware.

公开(公告)号：US20240256483A1

公开(公告)日：2024-08-01

申请号：US18415052

申请日：2024-01-17

申请人： Intel Corporation

发明人： Altug Koker ,  Varghese George ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Niranjan Cooray ,  Nicolas Galoppo Von Borries ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  David Puffer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Ankur N. Shah ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Saurabh Tangri

IPC分类号： G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

公开(公告)号：US20240241832A1

公开(公告)日：2024-07-18

申请号：US18097421

申请日：2023-01-16

申请人： Nokia Solutions and Networks Oy

发明人： Pranjal Kumar Dutta

IPC分类号： G06F12/0864 ,  G06F12/0895

CPC分类号： G06F12/0864 ,  G06F12/0895

摘要： Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to support a multi-mode indexed cache for a processor. Various example embodiments for supporting a multi-mode indexed cache for a processor may be configured to support a multi-mode indexed cache configured as a set associative cache having a plurality of sets, where the cache is configured to support multiple indexing modes for indexing memory blocks such that, for a memory operation for a memory block, the multiple indexing modes are configured to cause selection of different ones of the plurality of sets of the cache for the memory operation for the given memory block.

公开(公告)号：US12026099B2

公开(公告)日：2024-07-02

申请号：US17181879

申请日：2021-02-22

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Paul James Moyer

IPC分类号： G06F12/0895 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0866 ,  G06F12/0897

CPC分类号： G06F12/0895 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0897 ,  G06F12/0815 ,  G06F2212/1016 ,  G06F2212/1028

摘要： A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.

公开(公告)号：US12019514B2

公开(公告)日：2024-06-25

申请号：US17888590

申请日：2022-08-16

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： David Matthew Thompson ,  Abhijeet Ashok Chachad

IPC分类号： G06F11/10 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0879 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16 ,  H03M13/15

CPC分类号： G06F11/106 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/467 ,  G06F9/4812 ,  G06F9/52 ,  G06F11/1064 ,  G06F11/1068 ,  G06F12/0811 ,  G06F12/0879 ,  G06F12/0895 ,  G06F13/1668 ,  H03M13/1575 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/608

摘要： An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.

公开(公告)号：US12007935B2

公开(公告)日：2024-06-11

申请号：US17428523

申请日：2020-03-14

申请人： INTEL CORPORATION

发明人： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC分类号： G06F9/30 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Graphics processors and graphics processing units having dot product accumulate instructions for a hybrid floating point format are disclosed. In one embodiment, a graphics multiprocessor comprises an instruction unit to dispatch instructions and
a processing resource coupled to the instruction unit. The processing resource is configured to receive a dot product accumulate instruction from the instruction unit and to process the dot product accumulate instruction using a bfloat16 number (BF16) format.