公开(公告)号：US20140232445A1

公开(公告)日：2014-08-21

申请号：US13769406

申请日：2013-02-18

Applicant: APPLE INC.

Inventor： Bo Tang ,  Huaimin Li ,  Ajay Kumar Bhatia

IPC: H03K5/003

CPC classification number: H03K5/003 ,  H03K3/356104

Abstract: Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver. The input buffer may be configured to generate a buffered version and delayed inverted version of an external signal at a first voltage level. The voltage shift circuit may be configured to generate two internal signals at a second voltage level dependent upon the output signals of the input buffer. The output circuit may be configured to generate two output driver signals at the second voltage level dependent upon the output signals of the voltage shift circuit. The output driver circuit may be configured to generate an output signal at the second voltage level dependent on the two output driver signals.

Abstract translation: 公开了一种装置的实施例，其可以允许将信号从一个功率域转换到另一个功率域，并且在宽的工作范围内具有良好平衡的上升和下降时间。 该装置可以包括输入缓冲器，电压移位电路和输出电路以及输出驱动器。 输入缓冲器可以被配置为在第一电压电平下产生缓冲版本和外部信号的延迟反相版本。 电压移位电路可以被配置为根据输入缓冲器的输出信号产生处于第二电压电平的两个内部信号。 输出电路可以被配置为根据电压移位电路的输出信号产生处于第二电压电平的两个输出驱动器信号。 输出驱动器电路可以被配置为根据两个输出驱动器信号产生处于第二电压电平的输出信号。

公开(公告)号：US10241537B2

公开(公告)日：2019-03-26

申请号：US15622350

申请日：2017-06-14

Applicant: Apple Inc.

Inventor： Huaimin Li ,  Fabien S Faure ,  Shy Hamami ,  Pradeep Trivedi ,  Yaron Cohen

IPC: H03K3/017 ,  H03K5/156 ,  G01D5/24 ,  G06F1/08 ,  H03K21/08 ,  H03K5/04 ,  H03K5/00

Abstract: An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.

公开(公告)号：US20180364752A1

公开(公告)日：2018-12-20

申请号：US15622350

申请日：2017-06-14

Applicant: Apple Inc.

Inventor： Huaimin Li ,  Fabien S Faure ,  Shy Hamami ,  Pradeep Trivedi ,  Yaron Cohen

IPC: G06F1/08 ,  H03K3/017 ,  H03K21/08 ,  H03K5/04

CPC classification number: G06F1/08 ,  H03K3/017 ,  H03K5/04 ,  H03K21/08 ,  H03K2005/00019

Abstract: An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.

公开(公告)号：US08791743B1

公开(公告)日：2014-07-29

申请号：US13769406

申请日：2013-02-18

Applicant: Apple Inc.

Inventor： Bo Tang ,  Huaimin Li ,  Ajay Kumar Bhatia

IPC: H03L5/00

CPC classification number: H03K5/003 ,  H03K3/356104

Abstract: Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver. The input buffer may be configured to generate a buffered version and delayed inverted version of an external signal at a first voltage level. The voltage shift circuit may be configured to generate two internal signals at a second voltage level dependent upon the output signals of the input buffer. The output circuit may be configured to generate two output driver signals at the second voltage level dependent upon the output signals of the voltage shift circuit. The output driver circuit may be configured to generate an output signal at the second voltage level dependent on the two output driver signals.

Abstract translation: 公开了一种装置的实施例，其可以允许将信号从一个功率域转换到另一个功率域，并且在宽的工作范围内具有良好平衡的上升和下降时间。 该装置可以包括输入缓冲器，电压移位电路和输出电路以及输出驱动器。 输入缓冲器可以被配置为在第一电压电平下产生缓冲版本和外部信号的延迟反相版本。 电压移位电路可以被配置为根据输入缓冲器的输出信号产生处于第二电压电平的两个内部信号。 输出电路可以被配置为根据电压移位电路的输出信号产生处于第二电压电平的两个输出驱动器信号。 输出驱动器电路可以被配置为根据两个输出驱动器信号产生处于第二电压电平的输出信号。