公开(公告)号：US20180364752A1

公开(公告)日：2018-12-20

申请号：US15622350

申请日：2017-06-14

Applicant: Apple Inc.

Inventor： Huaimin Li ,  Fabien S Faure ,  Shy Hamami ,  Pradeep Trivedi ,  Yaron Cohen

IPC: G06F1/08 ,  H03K3/017 ,  H03K21/08 ,  H03K5/04

CPC classification number: G06F1/08 ,  H03K3/017 ,  H03K5/04 ,  H03K21/08 ,  H03K2005/00019

Abstract: An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.

公开(公告)号：US10241537B2

公开(公告)日：2019-03-26

申请号：US15622350

申请日：2017-06-14

Applicant: Apple Inc.

Inventor： Huaimin Li ,  Fabien S Faure ,  Shy Hamami ,  Pradeep Trivedi ,  Yaron Cohen

IPC: H03K3/017 ,  H03K5/156 ,  G01D5/24 ,  G06F1/08 ,  H03K21/08 ,  H03K5/04 ,  H03K5/00

Abstract: An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.