公开(公告)号：US20140173342A1

公开(公告)日：2014-06-19

申请号：US13713654

申请日：2012-12-13

Applicant: APPLE INC.

Inventor： Harshavardhan Kaushikkar ,  Muditha Kanchana ,  Gurjeet S Saund ,  Odutola O Ewedemi

IPC: G06F11/273

CPC classification number: G06F11/273 ,  G06F11/221 ,  G06F11/2236

Abstract: A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array.

Abstract translation: 相干系统包括可存储与处理器的高速缓冲存储器相关联的重复标签信息的存储阵列。 系统还可以包括流水线单元，其包括多个级以控制对存储阵列的访问。 流水线单元可以通过流水线阶段，而不产生对存储阵列的访问，即在结构上接收的输入/输出（I / O）请求。 该系统还可以包括可以将流水线单元的I / O请求重新格式化为调试请求的调试引擎。 调试引擎可以通过调试总线将调试请求发送到流水线单元。 响应于接收到调试请求，流水线单元可以访问存储阵列。 调试引擎可以通过结构总线返回到I / O请求的源，这是访问存储阵列的结果。

公开(公告)号：US09021306B2

公开(公告)日：2015-04-28

申请号：US13713654

申请日：2012-12-13

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Muditha Kanchana ,  Gurjeet S Saund ,  Odutola O Ewedemi

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22

CPC classification number: G06F11/273 ,  G06F11/221 ,  G06F11/2236

Abstract: A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array.

Abstract translation: 相干系统包括可存储与处理器的高速缓冲存储器相关联的重复标签信息的存储阵列。 系统还可以包括流水线单元，其包括多个级以控制对存储阵列的访问。 流水线单元可以通过流水线阶段，而不产生对存储阵列的访问，即在结构上接收的输入/输出（I / O）请求。 该系统还可以包括可以将流水线单元的I / O请求重新格式化为调试请求的调试引擎。 调试引擎可以通过调试总线将调试请求发送到流水线单元。 响应于接收到调试请求，流水线单元可以访问存储阵列。 调试引擎可以通过结构总线返回到I / O请求的源，这是访问存储阵列的结果。