公开(公告)号：US20250165747A1

公开(公告)日：2025-05-22

申请号：US19030867

申请日：2025-01-17

Applicant: APPLE INC.

Inventor： Erik Norden ,  Liran FISHEL ,  Sung Hee PARK ,  Jaewon SHIN ,  Christopher L. MILLS ,  Seungjin LEE ,  Fernando A. MUJICA

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.