公开(公告)号：US20250165747A1

公开(公告)日：2025-05-22

申请号：US19030867

申请日：2025-01-17

Applicant: APPLE INC.

Inventor： Erik Norden ,  Liran FISHEL ,  Sung Hee PARK ,  Jaewon SHIN ,  Christopher L. MILLS ,  Seungjin LEE ,  Fernando A. MUJICA

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20250060939A1

公开(公告)日：2025-02-20

申请号：US18452373

申请日：2023-08-18

Applicant: Apple Inc.

Inventor： Yildiz SINANGIL ,  Lei WANG ,  Michael L LIU ,  Jaewon SHIN

IPC: G06F7/544

Abstract: The present disclosure describes an in-memory computing (IMC) circuit including a first set of IMC cells having a first number of IMC cells and a second set of IMC cells having the first number of IMC cells. The first set of IMC cells can generate a first bit-product of a weight number having a first number of bits and a first bit of an input number having a second number of bits. The second set of IMC cells can generate a second bit-product of the weight number and a second bit of the input number. A first IMC cell of the first set of IMC cells includes a first bit-wise multiplication circuit configured to multiply a first bit of the weight number and the first bit of the input number.