公开(公告)号：US20170212758A1

公开(公告)日：2017-07-27

申请号：US15003828

申请日：2016-01-22

Applicant: ARM LIMITED

Inventor： Simon HOSIE ,  Jørn NYSTAD

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30021 ,  G06F9/3005 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384

Abstract: Various encoding schemes are discussed for more efficiently encoding instructions which identify first and second architectural register numbers. In the first example, by constraining the first architectural register number to be greater than the second architectural register number, this frees up encodings for use in encoding other operations. In a second example, the first and second architectural register numbers may take any value but one of a first type of processing operation and a second type of processing operation is selected depending on a comparison of the first and second architectural register numbers.

公开(公告)号：US20190087566A1

公开(公告)日：2019-03-21

申请号：US15705605

申请日：2017-09-15

Applicant: ARM LIMITED

Inventor： Simon HOSIE

IPC: G06F21/42 ,  G06F21/44 ,  G06F21/12 ,  G06F21/62

Abstract: A call path identifier is maintained which is permuted in response to a calling instruction for calling a target function, based on a function return address. The call path identifier is used as a modifier value for authentication code generating and checking instructions for generating and checking authentication codes associated with source values. In response to the authentication code checking instruction, if an expected authentication code mismatches a previously generated authentication code for a source value then an error handling response is triggered. This is useful for preventing attacks where address pointers which are valid in one part of the code are attempted to be reused in other parts of code.

公开(公告)号：US20170280307A1

公开(公告)日：2017-09-28

申请号：US15076903

申请日：2016-03-22

Applicant: ARM LIMITED

Inventor： Simon HOSIE

IPC: H04W4/16 ,  H04L5/00

CPC classification number: H04W4/16 ,  G06F11/0748 ,  H04L5/0053

Abstract: A data processing apparatus is provided. Call path storage circuitry stores an identifier of a call path and processing circuitry executes a current group of instructions from a plurality of groups of instructions. The processing circuitry is responsive to a calling instruction to firstly cause the processing circuitry to start executing, in dependence on the calling instruction, a next group of instructions from the plurality of groups of instructions such that the current group of instructions is added to the call path, and to secondly cause the call path storage circuitry to update the identifier of the call path, on the basis of the call path, using a compression algorithm.

公开(公告)号：US20170031682A1

公开(公告)日：2017-02-02

申请号：US14814582

申请日：2015-07-31

Applicant: ARM LIMITED

Inventor： Jacob EAPEN ,  Mbou EYOLE ,  Simon HOSIE

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032

Abstract: An apparatus comprises processing circuitry to generate a result vector including at least one N-bit data element in response to an element size increasing instruction identifying at least a first input vector including M-bit data elements, where N>M. First and second forms of the element size increasing instruction are provided for generating the result vector using first and second subsets of data elements of the first input vector respectively. Positions of the first and second subsets of data elements in the first input vector are interleaved.

Abstract translation: 一种装置包括处理电路，以响应于识别包括M位数据元素的至少第一输入向量的元素大小增加指令来生成包括至少一个N位数据元素的结果向量，其中N> M。 提供元素大小增加指令的第一和第二形式，用于分别使用第一输入向量的数据元素的第一和第二子集来生成结果向量。 数据元素的第一和第二子集在第一输入向量中的位置被交织。