公开(公告)号：US10176104B2

公开(公告)日：2019-01-08

申请号：US15281226

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Vasu Kudaravalli ,  Matthew Paul Elwood ,  Adam George ,  Muhammad Umar Farooq ,  Michael Filippo

IPC: G06F9/40 ,  G06F9/45 ,  G06F12/02 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/30 ,  G06F8/41

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.

公开(公告)号：US10289417B2

公开(公告)日：2019-05-14

申请号：US14519697

申请日：2014-10-21

Applicant: ARM LIMITED

Inventor： Michael Alan Filippo ,  Matthew Paul Elwood ,  Umar Farooq ,  Adam George

IPC: G06F9/30 ,  G06F9/38

Abstract: A data processing apparatus contains branch prediction circuitry including a micro branch target buffer, a full branch target buffer and a global history buffer. The branch target buffer entries contain history data which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry is suppressed for these following blocks of program instructions so as to save energy.

公开(公告)号：US10268581B2

公开(公告)日：2019-04-23

申请号：US15479348

申请日：2017-04-05

Applicant: ARM Limited

Inventor： Michael Filippo ,  Klas Magnus Bruce ,  Vasu Kudaravalli ,  Adam George ,  Muhammad Umar Farooq ,  Joseph Michael Pusdesris

IPC: G06F11/10 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0891

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.